| 賴飛羆 | Feipei Lai |
主要研究領域: Low Power SOC Design, Security
Major Research Areas: Low Power SOC Design, Security
| 研究領域摘要 |
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數位化資訊本身有著儲存成本低廉，複製容易，並且可以傳播快速即時等優勢，但是如何保護這些數位化資訊，以及規範其使用的方式，則成為一個相當重要的需求。 本計畫的著重數位權限管理技術的研發與系統整合的實作，使用這個系統的各個實體可以對包裹成數物件的資訊加以管制。我們整合權限控管技術，密碼技術，信號處理技術，設計一個完整，彈性，可攜，可擴充，與數位物件資料型態無關的數位權限管理系統，並開發新的系統架構，物件模型，授權程序，權限描述語言與權限處理機制。計畫最後，將完成核心的權限管理模組及展示用的數位資訊交流應用系統。 隨著可攜式裝置的普及化，如手機、手提式電腦、個人數位助理器等等，這些裝置對我們日常生活的影響也越來越大。然而、在不插電的狀況下，如何延長這些裝置的使用時間是非常重要的考量點。更重要的是，在下一代的中央處理器中，由於時脈不斷的提升，高速運算消耗大量功率引發中央處理器過熱的現象，也嚴重影響了電腦系統的穩定性及效能。本計劃的目的是針對由行為階層硬體描述語言所設計之電路進行功率分析與估計，並在最耗電部份進行改進，提出低功率高效能的計算機結構。 我們將在此計劃中首先實作一個功率估測器來分析行為階層硬體描述語言VHDL所設計之電路，最耗電的是那幾個部份，並估計整個電路的功率消耗情形，再針對幾個耗電嚴重的部份提出新的架構,並且將之轉換成為可合成的硬體描述語言暫存器轉移階層電路。近年來中央處理器的架構，首推管線電路，因此我們會以此架構為研究基礎。過去本實驗室已提出一個以機率為導向的分割演算法來二分割電路，在組合邏輯電路上，也獲得平均28.6%的省電效果。另一方面，利用多重分割演算法來降低功率消耗也已經有不錯的成果，最多可達到72%的省電效果。 |
| Research Summary |
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Digitized information has several advantages, including low storage cost, easy duplication, and rapid distribution. Recently, there has been a major demand that these digital data should be protected, and their usages should be controlled. In the project, we focus on developing digital rights management schemes, system integration and implementation. Each entity using the system can control the usages of the digital data packaged into digital objects. We make use of usage control techniques, cryptography, digital signal processing skills, and integrate them into the digital rights management system. The goal of the project is to design and implement an integrated, flexible, portable, and extensible digital rights management system, which works independently on the type of the digital information. New system framework, object model, licensing process, rights description language and rights management schemes are also developed. Finally, a core digital rights management module and a demonstrative digital information exchange application will be built. As the demand for the portable devices continuously increases in our daily life, such as cellular phone, PDA and notebook, low power design has become one of the major considerations for extending the operating time. Moreover, how to remove the heat in the high-speed computation systems to promote their performance and reliability is also an urgent problem. The objective of this project is to analyze and estimate the power of the behavioral level VHDL coded circuits, and then improve the most power consumption part to achieve a low-power high-performance architecture. In this project, we will first propose a new power estimator to analyze the behavioral level VHDL coded circuits to estimate the power dissipation of the whole circuit, and decide the most power consumption part. Second, in order to reach the low power goal, we will apply a new architecture to this part and transform it into a synthesizable RTL VHDL code. Recently, the pipelined architecture is the main trend of CPU design, we focus our design on the pipelined architecture basis. We have formulated the bipartition problem and presented a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation in pipelined circuits. Our experimental results show that an average power reduction on several MCNC benchmarks of 28.6% is achievable. Furthermore the cache memory is one of the main power dissipation portions of CPU. On the other hand, reduce power dissipation by using multipartition algorithm is also a competitive approach, the power reduction can be up to 72%. |
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| 主要著作 Selected Publications |
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