簡韶逸 Shao-Yi Chien

國立台灣大學電機工程學系 副教授
Associate Professor, Department of Electrical Engineering, National Taiwan University

主要研究領域:

多媒體訊號處理系統、多媒體積體電路設計、晶片系統設計方法研究

Major Research Areas:

Multimedia signal processing systems, multimedia VLSI design, and System-on-a-Chip design methodology

研究領域摘要:

簡教授主持媒體晶片系統實驗室。研究領域包括多媒體訊號處理系統、多媒體積體電路設計、以及晶片系統設計方法研究，從演算法層次涵括到硬體晶片設計層次到系統設計層次。近年之研究重點為智慧型視訊處理系統、影像信號處理系統、繪圖晶片設計、以及數位電視晶片設計。

Research Summary:

Prof. Chien directs Media IC & System Design Lab. The research area includes multimedia signal processing systems, multimedia VLSI design, and System-on-a-Chip design methodology. The research level is from algorithm level, hardware architecture level, to system level. The current research directions of Media IC & System Design Lab are intelligent video signal processing systems, image signal processing systems, graphics processing unit design, and digital TV chipset design
Photo of Shao-Yi Chien

代表性著作 Selected Publication

  1. Shao-Yi Chien, You-Ming Tsao, Chin-Hsiang Chang, and Yu-Cheng Lin, “An 8.6mW 25Mvertices/s 400-MFLOPS 800-MOPS 8.91mm2 multimedia stream processor core for mobile applications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2025-2035, Sept. 2008
  2. Jason C. Chen and Shao-Yi Chien, “CRISP: coarse-grained reconfigurable image stream processor for digital still cameras and camcorders,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 18. no. 9, pp. 1223-1236, Sept. 2008
  3. Jason C. Chen, Chun-Fu Shen, and Shao-Yi Chien, “Coarse-grained reconfigurable image stream processor for digital still cameras and camcorders,” Proc. of IEEE Custom Integrated Circuits Conference (CICC2007), San Jose, USA, Sept. 2007
  4. You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin, Shao-Yi Chien, and Liang-Gee Chen, “An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 stream processor core for mobile graphics and video applications,” Digest of Technical Papers of Symposium on VLSI Circuits, Kyoto, Japan, Jun. 2007
  5. Li-Fu Ding, Shao-Yi Chien, and Liang-Gee Chen, “Joint prediction algorithm and architecture for stereo video hybrid coding systems,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 11, pp. 1324--1337, Nov. 2006
  6. Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, and Liang-Gee Chen, “Hybrid morphology processing unit architecture for moving object segmentation systems,” Journal of VLSI Signal Processing, vol. 42, no. 3, pp. 241-255, Mar. 2006
  7. Shao-Yi Chien, Shyh-Yih Ma, and Liang-Gee Chen, “Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 9, pp. 1156--1169, Sept. 2005
  8. Shao-Yi Chien, Yu-Wen Huang, Ching-Yeh Chen, Homer H. Chen, and Liang-Gee Chen, “Hardware architecture design of video compression for multimedia communication systems,” IEEE Communications Magazine, vol. 43, no. 8, pp. 122--131, Aug. 2005
  9. Shao-Yi Chien, Yu-Wen Huang, Bing-Yu Hsieh, Shyh-Yih Ma, and Liang-Gee Chen, “Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques,” IEEE Transactions on Multimedia, vol. 6, no. 5, pp. 732-748, Oct. 2004
  10. Shao-Yi Chien, Yu-Wen Huang, and Liang-Gee Chen, “Predictive watershed: a fast watershed algorithm for video segmentation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 5, May 2003, pp. 453-461, May 2003
  11. Shao-Yi Chien, Shyh-Yih Ma, and Liang-Gee Chen, “Efficient moving object segmentation algorithm using background registration technique,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 7, pp. 577-586, Jul. 2002