陳少傑 Sao-Jie Chen
國立台灣大學電機工程學系 教授
Professor, Department of Electrical Engineering, National Taiwan University
主要研究領域:
無線電路設計及軟硬體共同設計Major Research Areas:
Wireless Circuits & HW-SW Co-Design研究領域摘要:
1. 無線電路設計
2. 實體設計自動化
3. SOC軟硬體共同設計
Research Summary:
1. Wireless LAN and Bluetooth Circuits Design
2. Physical Design Automation
3. SOC Hardware-Software Codesign
-
B.S.
EE, National Taiwan University , 1977 -
M.S.
EE, National Taiwan University , 1982 -
Ph.D.
EE, Southern Methodist University , 1988
-
Address
EE2-417,
Department of Electrical Engineering,
National Taiwan University,
Taipei 106, Taiwan -
Phone
+886-2-33663647 -
FAX
+886-2-23638247 -
Email:
-
Lab. Homepage:
代表性著作 Selected Publication
- B. S. Lin, B. S. Lin, N. K. Chou, F. C. Chong, and S. J. Chen, “RTWPMS: a Real-Time Wireless Physiological Monitoring System,” IEEE Transactions on Information Technology in Biomedicine, Vol. 10, No. 4, pp. 647-656, Oct. 2006
- Y. H. Hsieh, W. Y. Hu, S. M. Lin, C. L. Chen, W. K. Li, S. J. Chen, D. J. Chen, “An Auto-I/Q Calibrated CMOS Transceiver for 802.11g,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 11, pp. 2187-2192, Nov. 2005
- Y. H. Hsieh, W. Y. Hu, W. K. Li, S. M. Lin, C. L. Chen, D. J. Chen, and S. J. Chen, “A 6.25mm2 2.4GHz CMOS 802.11b Transceiver,” IEICE Trans. Electronics, Vol.E88-C No.8, pp.1723-1725, Aug. 2005
- T. Y. Ho, Y. W. Chang, S. J. Chen, and D. T. Lee, “Crosstalk- and Performance-Driven Multilevel Full-Chip Routing,” IEEE Trans. on Computer-Aided Design, Vol. 24, No. 6, pp. 869-878, Jun. 2005
- C. W. Chang, M. F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C. K, Cheng, and S. J. Chen, “Fast Post-Placement Optimization Using Functional Symmetries,” IEEE Trans. on Computer-Aided design, Vol. 23, No. 1, pp. 102-118, Jan. 2004
- J. P. Fang, Y. S. Tong, and S. J. Chen, “Simultaneous Routing and Buffering in SOC Floorplan Design,” IEE Proceedings-Computers and Digital Techniques, Vol. 151, No. 1, pp. 17-22, Jan. 2004