黃俊郎 Jiun-Lang Huang

國立台灣大學電機工程學系 教授
Professor, Department of Electrical Engineering, National Taiwan University

主要研究領域:

超大型積體電路的自我測試與缺陷容忍、高速I/O界面的測試技術、低功率測試

Major Research Areas:

VLSI Self-Testing and Fault-Tolerance, High-Speed I/O Testing, Power-Save Testing

研究領域摘要:

本實驗室的研究領域為:(1)超大型積體電路的自我測試與缺陷容忍、(2)高速I/O界面的測試技術、與(3)低功率測試

目前的研究題目包括
1. ADC/DAC design-for-test and built-in-self-test
2. ADC/DAC external digital calibration
3. Jitter tolerance testing
4. Jitter extraction and decomposition
5. Low power test pattern generation and compression
6. Design for low test power

Research Summary:

The  research areas include (1) VLSI Self-Testing and Fault-Tolerance, (2) High-Speed I/O Testing, and (3) Power-Safe Testing.

Current research topics are
1. ADC/DAC design-for-test and built-in-self-test
2. ADC/DAC external digital calibration
3. Jitter tolerance testing
4. Jitter extraction and decomposition
5. Low power test pattern generation and compression
6. Design for low test power

Photo of Jiun-Lang Huang