黃鐘揚 Chung-Yang Huang

國立台灣大學電機工程學系 教授
國立台灣大學電子工程學研究所副教授
Professor, Department of Electrical Engineering, National Taiwan University
Associate Professor, Graduate Institute of Electronics Engineering, National Taiwan University

主要研究領域:

(1) SoC電路設計驗證, (2) 電路設計自動化及最佳化, (3) 可驗證性電路設計, (4) Constraint Satisfication問題

Major Research Areas:

(1) design verification for SoCs, (2) design for verifiability, (3) design automation and optimization, and (4) constraint satisfaction problems in electronic design automation (EDA) area.

研究領域摘要:

可靠性系統實驗室(三) 設計驗證工作室

本實驗室主要之研究領域為晶片系統(SoC)之設計驗證,其中的項目包括:

  1. 核心驗證引擎之研究與開發
  2. 網路、通訊、多媒體智財(IP)之驗證技術
  3. 系統設計分析與除錯技術
  4. Constraint Satisfaction Problem (CSP) 之各項應用。

綜合以上之研究,本實驗室正著手開發兩套驗證工具系統:

  1. Property Verification Framework
  2. IP Qualification Framework

Research Summary:

Lab of Dependable Systems (3) Design Verification Team

The research focus of our lab is in the SoC (System on a Chip) design verification area, which includes:

  1. Sequential verification engines (e.g. ATPG, SAT, BDD, Arithmetic solver, etc)
  2. Network, communication, and multimedia IP verification techniques
  3. Design for Verifiability (DfV)
  4. System design analysis and debugging techniques
  5. Various applications of Constraint Satisfaction Problem (CSP)

We are implementing the above research topics into our own tools:

  1. Property Verification Framework
  2. IP Qualification Framework
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