江介宏教授的著作列表 - Publication List of Jie-Hong Roland Jiang

Publication List of 江介宏 Jie-Hong Roland Jiang

Journal articles & book chapters:

  1. Yu-Shan Huang, Jie-Hong R. Jiang, “Circuit Learning: From Decision Trees to Decision Graphs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, 3985-3996, Nov. 2023
  2. Yun-Rong Luo, Che Cheng,Jie-Hong R. Jiang, “A Resolution Proof System for Dependency Stochastic Boolean Satisfiability,” Journal of Automated Reasoning, 67, Aug. 2023
  3. Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko, “Quantized Neural Network Synthesis for Direct Logic Circuit Implementation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, 473-482, Feb. 2023
  4. Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken, “Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 12, 584-601, Sept. 2022
  5. Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken, “Design and Automation for Quantum Computation and Quantum Technologies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 12, 581-583, Sept. 2022
  6. Kuan-Hua Tu, Hung-En Wang, Jie-Hong R. Jiang, Natalia Kushik, Nina Yevtushenko, “Homing Sequence Derivation With Quantified Boolean Satisfiability,” IEEE Transactions on Computers, 71, 696-711, Mar. 2022
  7. Nian-Ze Lee, Jie-Hong R. Jiang, “Constraint Solving for Synthesis and Verification of Threshold Logic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40, 904-917, May 2021
  8. He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang, “SAT-Based On-Track Bus Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40, 735-747, Apr. 2021
  9. Chia-Chih Chi, Jie-Hong R. Jiang, “Logic synthesis of binarized neural networks for efficient circuit implementation,” Proceedings of the International Conference on Computer-Aided Design, undefined, 1-7, Nov. 2018
  10. Nian-Ze Lee, Jie-Hong R. Jiang, “Towards Formal Evaluation and Verification of Probabilistic Design,” IEEE Trans. Computers, 67(8), 1202-1216, Aug. 2018
  11. Tai-Yin Chiu and Jie-Hong R. Jiang, “Logic Synthesis of Recombinase Based Genetic Circuits,” Scientific Reports, 7, Article No. 12873, doi:10.1038/s41598-017-07386-3, Oct. 2017
  12. Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong R. Jiang, “A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning,” IEEE Trans. on CAD of Integrated Circuits and Systems, 36(8): 1251-1264, Aug. 2017
  13. Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang, “Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(11): 1797-1810, Nov. 2016
  14. Valeriy Balabanov, Shuo-Ren Lin, and Jie-Hong R. Jiang, “Flexibility and Optimization of QBF Skolem-Herbrand Certificates,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(9): 1557-1568, Sept. 2016
  15. Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang, “Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(4): 598-610, Apr. 2016
  16. Nina Yevtushenko, Khaled El-Fakih, Tiziano Villa, Jie-Hong R. Jiang, “Deriving Compositionally Deadlock-free Componenets over Synchronous Automata Compositions,” The Computer Journal, 58(11): 2793-2803, Nov. 2015
  17. Tai-Yin Chiu, Hui-Ju K. Chiang, Ruei-Yang Huang, Jie-Hong R. Jiang, François Fages, “Synthesizing Configurable Biochemical Implementation of Linear Systems from Their Transfer Function Specifications,” PLOS ONE, 10(9): e0137442, Sept. 2015
  18. Hui-Ju Katherine Chiang, Francois Fages, Jie-Hong Roland Jiang, and Sylvain Soliman, “Hybrid Simulations of Heterogeneous Biochemical Models in SBML,” ACM Trans. Model. Comput. Simul., 25(2):14, Feb. 2015
  19. Valeriy Balabanov, Hui-Ju K. Chiang, and Jie-Hong R. Jiang, “Henkin quantifiers and Boolean formulae: A certification perspective of DQBF,” Theoretical Computer Science (TCS), 523(2), pp. 86-100, Feb. 2014
  20. Tsung-Po Liu, Shuo-Ren Lin, and Jie-Hong R. Jiang, “Software Workarounds for Hardware Errors: Instruction Patch Synthesis,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 32(12), pp. 1992-2003, Dec. 2013
  21. Yi-Ting Chung and Jie-Hong R. Jiang, “Functional Timing Analysis Made Fast and General,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 32(9), pp. 1421-1434, Sept. 2013
  22. Kuan-Hsien Ho, Jie-Hong R. Jiang, and Yao-Wen Chang, “TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders,” IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD), 31(11), pp. 1723-1733, Nov. 2012
  23. Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, and Jie-Hong R. Jiang, “Automatic Decoder Synthesis: Methods and Case Studies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(9), pp. 1319-1331, Sept. 2012
  24. Valeriy Balabanov and Jie-Hong R. Jiang, “Unified QBF Certification and its Applications,” Formal Methods in System Design (FMSD), 41(1), pp. 45-65, Aug. 2012
  25. Alan Mishchenko, Robert Brayton, Jie-Hong R. Jiang, and Stephen Jang, “Scalable Don't-Care-Based Logic Optimization and Resynthesis,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), 4(4):34, Dec. 2011
  26. Jie-Hong Roland Jiang, Hsuan-Po Lin, and Wei-Lun Hung, “Extracting Functions from Boolean Relations Using SAT and Interpolation,” Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati, editors, Springer, (book chapter, pages 287-307), 2011
  27. Ruei-Rung Lee, Jie-Hong Roland Jiang, and Wei-Lun Hung, “Bi-decomposition Using SAT and Interpolation,” Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati, editors, Springer, (book chapter, pages 87-105), 2011
  28. Hsuan-Po Lin, Jie-Hong Roland Jiang, and Ruei-Rung Lee, “Ashenhurst Decomposition Using SAT and Interpolation,” Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati, editors, Springer, (book chapter, pages 67-85), 2011
  29. Jie-Hong R. Jiang and Tiziano Villa, “Hardware Equivalence and Property Verification,” Boolean Methods and Models in Mathematics, Computer Science and Engineering, Y. Crama and P. L. Hammer, editors, Cambridge University Press, (book chapter, pages 599-674), May 2010
  30. Jie-Hong R. Jiang, Chih-Chun Lee, Alan Mishchenko, and Chung-Yang Huang, “To SAT or Not to SAT: Scalable Exploration of Functional Dependency,” IEEE Transactions on Computers (TCOM), vol. 59, no. 4, pages 457-467, Apr. 2010
  31. Jie-Hong R. Jiang and Srinivas Devadas, “Logic Synthesis in a Nutshell,” Electronic Deisng Automation: Synthesis, Verification, and Test, Wang et al., editors, Morgan Kaufmann Publishers, (book chapter, pages 299-404), 2009
  32. Jie-Hong R. Jiang, Dah-Wei Chiou, and Cheng-En Wu, “Quantum Mechanical Search and Harmonic Perturbation,” Quantum Information Processing, vol. 6, issue 5, pages 349-362, Oct. 2007
  33. Jie-Hong R. Jiang and Robert K. Brayton, “Retiming and Resynthesis: A Complexity Perspective,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 12, pages 2674-2686, Dec. 2006
  34. Jie-Hong R. Jiang and Robert K. Brayton, “On the Verification of Sequential Equivalence,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 22, no. 6, pages 686-697, Jun. 2003

Conference & proceeding papers:

  1. Che Cheng, Yun-Rong Luo, Jie-Hong R. Jiang, “Knowledge Compilation for Incremental and Checkable Stochastic Boolean Satisfiability,” 33rd International Joint Conference on Artificial Intelligence (IJCAI), 1862-1872, Jeju, South Korea, Aug. 2024
  2. Tian-Fu Chen, Jie-Hong R. Jiang, “Boolean Matching Reversible Circuits: Algorithm and Complexity,” 61st ACM/IEEE Design Automation Conference (DAC), 1-6, San Francisco CA USA, Jun. 2024
  3. Wei-Hsiang Tseng,Chang,Jiang, “Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems,” International Symposium on Physical Design (ISPD), 245-253, Taipei Taiwan, Mar. 2024
  4. Yu-Wei Fan, Jie-Hong R. Jiang, “Unifying Decision and Function Queries in Stochastic Boolean Satisfiability,” 38th AAAI Conference on Artificial Intelligence (AAAI), 7995-8003, Vancouver, Canada, Feb. 2024
  5. Kuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan,Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang, “WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, San Francisco, CA, USA, Oct. 2023
  6. Tian-Fu Chen, Chun-Yu Wei, Jie-Hong R. Jiang, “VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion,” IEEE International Conference on Quantum Computing and Engineering (QCE), 1033-1043, Bellevue, WA, USA, Sept. 2023
  7. Chun-Yu Wei, Jie-Hong R. Jiang, “Don’t-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration,” 60th ACM/IEEE Design Automation Conference (DAC), 1-6, San Francisco, CA, USA, Jul. 2023
  8. Che Cheng, Jie-Hong R. Jiang, “Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT,” 37th AAAI Conference on Artificial Intelligence (AAAI), 3906-3914, Washington, DC, USA, Feb. 2023
  9. Yu-Wei Fan, Jie-Hong R. Jiang, “SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver,” 37th AAAI Conference on Artificial Intelligence (AAAI), 3949-3958, Washington, DC, USA, Feb. 2023
  10. Jie-Hong R. Jiang, “Second-Order Quantified Boolean Logic,” 37th AAAI Conference on Artificial Intelligence (AAAI), 4007-4015, Washington, DC, USA, Feb. 2023
  11. Chang-Jun Wang, Jie-Hong R. Jiang, “Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification,” IEEE Biomedical Circuits and Systems Conference (BioCAS), 120-124, Taipei, Taiwan, Oct. 2022
  12. Wan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang, “Language Equation Solving via Boolean Automata Manipulation,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-9, San Diego, California, Oct. 2022
  13. Tian-Fu Chen, Jie-Hong R. Jiang, Min-Hsiu Hsieh, “Partial Equivalence Checking of Quantum Circuits,” IEEE International Conference on Quantum Computing and Engineering (QCE), 594-604, Broomfield, CO, USA, Sept. 2022
  14. Hao-Ren Wang, Kuan-Hua Tu, Jie-Hong R. Jiang, Christoph Scholl, “Quantifier Elimination in Stochastic Boolean Satisfiability,” International Conference on Theory and Applications of Satisfiability Testing (SAT), 23:1-23:17, Haifa, Israel, Aug. 2022
  15. Chun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang, “Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification,” 59th ACM/IEEE Design Automation Conference, 523-528, San Francisco California, Jul. 2022
  16. Cheng-Han Hsieh, Jie-Hong R. Jiang, “Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability,” Thirty-First International Joint Conference on Artificial Intelligence {IJCAI-22}, 1834-1842, Vienna, Austria, Jul. 2022
  17. Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang, “Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation,” 58th ACM/IEEE Design Automation Conference (DAC), 439-444, San Francisco, CA, USA, Dec. 2021
  18. He-Teng Zhang, Jie-Hong R. Jiang, Luca Amarú, Alan Mishchenko, Robert Brayton, “Deep Integration of Circuit Simulator and SAT Solver,” 58th ACM/IEEE Design Automation Conference (DAC), 877-882, San Francisco, CA, USA, Dec. 2021
  19. Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong R. Jiang, Chung-Yang Huang, “Compatible Equivalence Checking of X-Valued Circuits,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, Munich, Germany, Nov. 2021
  20. He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko, “A Circuit-Based SAT Solver for Logic Synthesis,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, Munich, Germany, Nov. 2021
  21. Pei-Wei Chen, Yu-Ching Huang, Jie-Hong R. Jiang, “A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving,” 35th AAAI Conference on Artificial Intelligence (AAAI), 3697-3706, Virtual, Feb. 2021
  22. Nian-Ze Lee, Jie-Hong R. Jiang, “Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty,” 35th AAAI Conference on Artificial Intelligence (AAAI), 3877-3885, Virtual, Feb. 2021
  23. Rai et al., “Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 1026-1031, Grenoble, France, Feb. 2021
  24. Yu-Chou Lin, Jie-Hong R. Jiang, “Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, San Diego, CA, USA, Nov. 2020
  25. Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets, “Symbolic uniform sampling with XOR circuits,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-9, San Diego, CA, USA, Nov. 2020
  26. Pei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong R. Jiang, “Circuit Learning for Logic Regression on High Dimensional Boolean Space,” 57th ACM/IEEE Design Automation Conference (DAC), 1-6, San Francisco, CA, USA, Jul. 2020
  27. Po-Chun Chien, Jie-Hong R. Jiang, “Time Multiplexing via Circuit Folding,” 57th ACM/IEEE Design Automation Conference (DAC), 1-6, San Francisco, CA, USA, Jul. 2020
  28. He-Teng Zhang, Jie-Hong R. Jiang, “SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies,” 57th ACM/IEEE Design Automation Conference (DAC), 1-6, San Francisco, CA, USA, Jul. 2020
  29. Min Hao Peng, Fang Yu, Jie-Hong R. Jiang, “Symbolic Gas Vulnerability Detection and Attack Synthesis,” Pacific Asia Conference on Information Systems, Dubai, Jun. 2020
  30. Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee, “Engineering Change Order for Combinational and Sequential Design Rectification,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 726-731, Grenoble, France, Mar. 2020
  31. Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener, “Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 738-743, Grenoble, France, Mar. 2020
  32. Po-Chun Chien, Jie-Hong R. Jiang, “Time-Frame Folding: Back to the Sequentiality,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, Westminster, CO, USA, Nov. 2019
  33. Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang, “Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, Westminster, CO, USA, Nov. 2019
  34. Li-Cheng Chen, Jie-Hong R. Jiang, “A Cube Distribution Approach to QBF Solving and Certificate Minimization,” International Conference on Principles and Practice of Constraint Programming (CP 2019), 529-546, Stamford, CT, U.S., Oct. 2019
  35. Victor N. Kravets, Nian-Ze Lee and Jie-Hong R. Jiang, “Comprehensive Search for ECO Rectification Using Symbolic Sampling,” 56th ACM/IEEE Design Automation Conference (DAC), 1-6, Las Vegas, NV, USA, Jun. 2019
  36. Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang, “Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis,” 56th ACM/IEEE Design Automation Conference (DAC), 1-6, Las Vegas, NV, USA, Jun. 2019
  37. Zi-Jun Lin,Wei-Chih Huang, Jie-Hong R. Jiang, “Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits,” IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 200-205, Fredericton, NB, Canada, May 2019
  38. Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang, “An approximation algorithm to the optimal switch control of reconfigurable battery packs,” In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), 577-584, Tokyo, Japan, Jan. 2019
  39. Christoph Scholl, Jie-Hong R. Jiang, Ralf Wimmer, Aile Ge-Ernst, “A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving,” In Proc. AAAI Conference on Artificial Intelligence (AAAI), Honolulu, USA, Jan. 2019
  40. Yi-Fan Evan Chang,Ruei-Yang Huang, Jie-Hong R. Jiang, “Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits,” 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 19-26, Hirosaki, Japan, 2019
  41. Wei-Chih Huang, Jie-Hong R. Jiang, Francois Fages, Franck Molina, “Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity,” 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, Nara, Japan, 2019
  42. S.-Y. Lee, N.-Z. Lee, J.-H. R. Jiang, “Canonicalization of Threshold Logic Representation and its Applications,” In Proc. Int’l Conf. on Computer-Aided Design (ICCAD), 85:1-85:8, San Diego, USA, Nov. 2018
  43. C.-C. Chi, J.-H. R. Jiang, “Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation,” In Proc. Int’l Conf. on Computer-Aided Design (ICCAD), 84:1-84:7, San Diego, USA, Nov. 2018
  44. H.-E. Wang, S.-Y. Chen, F. Yu, J.-H. R. Jiang, “A Symbolic Model Checking Approach to the Analysis of String and Length Constraints,” In Proc. International Conference on Automated Software Engineering (ASE), 623-633, Montpellier, France, Sept. 2018
  45. N.-Z. Lee, Y.-S. Wang, J.-H. R. Jiang, “Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection,” In Proc. International Joint Conference on Artificial Intelligence (IJCAI), 1339-1345, Stockholm, Sweden, Jul. 2018
  46. H.-T. Zhang, J.-H. R. Jiang, “Cost-Aware Patch Generation for Multi-Target Function Rectification of Engineering Change Orders,” In Proc. Design Automation Conference (DAC), 96:1-96:6, San Francisco, USA, Jun. 2018
  47. A. Q. Dao, N.-Z. Lee, L.-C. Chen, P.-H. Lin, J.-H. R. Jiang, A. Mishchenko, R. K. Brayton, “Efficient Computation of ECO Patch Functions,” In Proc. Design Automation Conference (DAC), 51:1-51:6, San Francisco, USA, Jun. 2018
  48. R.-Y. Wang, C.-C. Pai, J.-J. Wang, H.-T. Wen, Y.-C. Pai, Y.-W. Chang, C.-M. Li, J.-H. R. Jiang, “Efficient Multi-Layer Obstacle-Avoiding Region-to-Region Rectilinear Steiner Tree Construction,” In Proc. Design Automation Conference (DAC), 45:1-45:6, San Francisco, USA, Jun. 2018
  49. C.-H. Lin, F. Yu, J.-H. R. Jiang, T. Bultan, “Static Detection of API Call Vulnerabilities in iOS Executables,” In Proc. International Conference on Software Engineering (ICSE) (Companion Volume), 394-395, Gothenburg, Sweden, May 2018
  50. Nian-Ze Lee, Victor Kravets, and Jie-Hong R. Jiang, “Sequential Engineering Change Order under Retiming and Resynthesis,” In Proc. International Conference on Computer-Aided Design (ICCAD), Irvine, California USA, Nov. 2017
  51. Hung-En Wang, Kuan-Hua Tu, Jie-Hong R. Jiang, and Natalia Kushik, “Homing Sequence Derivation with Quantified Boolean Satisfiability,” In Proc. IFIP International Conference on Testing of Software and Systems (ICTSS), Saint Petersburg, Russia, Oct. 2017
  52. Chun-Ning Lai, Jie-Hong Jiang, and Francois Fages, “RecombinaseBased Genetic Circuit Optimization,” In Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, Oct. 2017
  53. Nian-Ze Lee, Yen-Shi Wang, and Jie-Hong R. Jiang, “Solving Stochastic Boolean Satisfiability under Random-Exist Quantification,” In Proc. International Joint Conferences on Artificial Intelligence (IJCAI), Melbourne, Australia, Aug. 2017
  54. Chun-Ning Lai and Jie-Hong R. Jiang, “Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation,” In Proc. Design Automation Conference (DAC), Austin, Texas USA, Jun. 2017
  55. Cheng-Yu Shih, Chun-Hong Shih, and Jie-Hong R. Jiang, “Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits,” In Proc. Design Automation Conference (DAC), Austin, Texas USA, Jun. 2017
  56. Chun-Hong Shih and Jie-Hong Roland Jiang, “Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines,” In Proc. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), San Diego, California USA, May 2017
  57. Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, and Jie-Hong R. Jiang, “Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits,” In Proc. International Conference on Computer-Aided Design (ICCAD), Austin, Texas USA, Nov. 2016
  58. Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton, “2QBF: Challenges and Solutions,” Proc. Int'l Conf. on Theory and Applications of Satisfiability Testing (SAT), pages 453-469, Bordeaux, France, Jul. 2016
  59. Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang, “String Analysis via Automata Manipulation with Logic Circuit Representation,” Proc. Int'l Conf. on Computer Aided Verification (CAV), vol. 1, pages 241-260, Toronto, Canada, Jul. 2016
  60. Grace Wu, Yi-Tin Sun, and Jie-Hong R. Jiang, “Design Partitioning for Large Scale Equivalence Checking and Functional Correction,” Proc. Design Automation Conference (DAC), 23:1-23:6, Austin, TX, USA, Jun. 2016
  61. Yi-Hsiang Lai, Chi-Chuan Chuang, and Jie-Hong R. Jiang, “A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines,” Proc. International Conference on Computer- Aided Design (ICCAD), Austin, TX, USA, Nov. 2015
  62. Ting-Wei Chiang and Jie-Hong R. Jiang, “Property-Directed Synthesis of Reactive Systems from Safety Specications,” Proc. International Conference on Computer- Aided Design (ICCAD), Austin, TX, USA, Nov. 2015
  63. Chun-Hong Shih, Yi-Hsiang Lai, and Jie-Hong R. Jiang, “SPOCK: Static Performance analysis and deadlOCK verication for ecient asynchronous circuit synthesis,” Proc. International Conference on Computer- Aided Design (ICCAD), Austin, TX, USA, Nov. 2015
  64. Bo-Yuan Huang, Yi-Hsiang Lai, and Jie-Hong R. Jiang, “Asynchronous QDI Circuit Synthesis from Signal Transition Protocols,” Proc. International Conference on Computer- Aided Design (ICCAD), Austin, TX, USA, Nov. 2015
  65. Kuan-Hua Tu, Tzu-Chen Hsu, and Jie-Hong R. Jiang, “QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving,” Proc. International Conference on Theory and Applications of Satisfiability Testing (SAT), Austin, TX, USA, Sept. 2015
  66. Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, and Francois Fages, “Recongurable Neuromorphic Computation in Biochemical Systems,” Proc. Int'l Conf. of the IEEE Engineering in Medicine and Biology Society (EMBC), Milan, Italy, Aug. 2015
  67. Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, and Jie-Hong R. Jiang, “Scalable Sequence-Constrained Retention Register Minimization in Power Gating Design,” Proc. ACM/IEEE Design Automation Conference (DAC), 130:1-130:6, San Francisco, CA, USA, Jun. 2015
  68. Valeriy Balabanov, Jie-Hong R. Jiang, Mikolas Janota, and Magdalena Widl, “Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs,” Proc. AAAI Conference on Artificial Intelligence (AAAI-15), pp. 3694-3701, Austin, TX, USA, Jan. 2015
  69. Nian-Ze Lee and Jie-Hong R. Jiang, “Towards Formal Evaluation and Verification of Probabilistic Design,” Proc. International Conference on Computer- Aided Design (ICCAD), pp. 340-347, San Jose, CA, USA, Nov. 2014
  70. Hui-Ju Katherine Chiang, Jie-Hong Roland Jiang, and François Fages, “Building Reconfigurable Circuitry in a Biochemical World,” Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 560-563, Lausanne, Switzerland, Oct. 2014
  71. Valeriy Balabanov, Magdalena Widl, and Jie-Hong R. Jiang, “QBF Resolution Systems and their Proof Complexities,” Proc. International Conference on Theory and Applications of Satisfiability Testing (SAT), pp. 154-169, Vienna, Austria, Jul. 2014
  72. Tai-Yin Chiu, Ruei-Yang Huang, Hui-Ju K. Chiang, Jie-Hong R. Jiang, and François Fages, “Configurable Linear Control of Biochemical Systems,” Proc. International Workshop on Bio-Design Automation (IWBDA), Boston, MA, USA, Jun. 2014
  73. Chi-Yuan Liu, Hui-Ju K. Chiang, Yao-Wen Chang, and Jie-Hong R. Jiang, “Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification,” Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2014
  74. Chi-Chuan Chuang, Yi-Hsiang Lai, and Jie-Hong R. Jiang, “Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits,” Proc. ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Jun. 2014
  75. Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, and Chien-Mo James Li, “Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 91-98, San Jose, CA, USA, Nov. 2013
  76. Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, and Meng-Yen Li, “Encoding Multi-Valued Functions for Symmetry,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 771-778, San Jose, CA, USA, Nov. 2013
  77. Georg Hofferek, Ashutosh Gupta, Bettina Konighofer, Jie-Hong Roland Jiang, and Roderick Bloem, “Synthesizing Multiple Boolean Functions Using Interpolation on a Single Proof,” Proc. International Conference on Formal Methods in Computer-Aided Design (FMCAD), pp. 77-84, Portland, OR, USA, Oct. 2013
  78. Hui-Ju Katherine Chiang, Francois Fages, Jie-Hong R. Jiang, Sylvain Soliman, “On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models,” Prof. International Conference on Computational Methods in Systems Biology (CMSB), pp. 192-205, Klosterneuburg, Austria, Sept. 2013
  79. Ruei-Yang Huang, De-An Huang, Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, and Francois Fages, “Species Minimization in Computation with Biochemical Reactions,” Proc. International Workshop on Bio-Design Automation (IWBDA), London, UK, Jul. 2013
  80. Kuan-Hua Tu and Jie-Hong R. Jiang, “Synthesis of feedback decoders for initialized encoders,” Proc. ACM/IEEE Design Automation Conference (DAC), Austin, TX, USA, Jun. 2013
  81. De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng, “Compiling Program Control Flows into Biochemical Reactions,” Proc. Int'l Conf. on Computer-Aided Design (ICCAD'12), pages 361-368, San Jose, CA, USA, Nov. 2012
  82. Kai-Hui Chang, Chia-Wei Chang, Jie-Hong R. Jiang, and Chien-Nan Jimmy Liu, “Improving Design Verifiability by Early RTL Coverability Analysis,” Proc. ACM/IEEE International Conference on Formal Methods and Models for Codesign(MEMOCODE'12), pages 25-32, Arlington, VA, USA, Jul. 2012
  83. Cheng-Shen Han and Jie-Hong R. Jiang, “When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way,” Proc. International Conference on Computer Aided Verification (CAV'12), pages 410-426, Berkeley, USA, Jul. 2012
  84. Valeriy Balabanov, Hui-Ju Katherine Chiang, and Jie-Hong R. Jiang, “Henkin Quantifiers and Boolean Formulae,” Proc. Int'l Conference on the Theory and Applications of Satisfiability Test (SAT'12), pages 129-142, Trento, Italy, Jun. 2012
  85. Yi-Ting Chung and Jie-Hong R. Jiang, “Functional Timing Analysis Made Fast and General,” Proc. ACM/IEEE Design Automation Conference (DAC'12), pages 1055-1060, San Francisco, USA, Jun. 2012
  86. Yi-Ting Chung and Jie-Hong R. Jiang, “Efficient Transformation of Various Timed Characteristic Functions for Satisfiability Solving,” Proc. Int'l Workshop on Logic and Synthesis (IWLS'12), Berkeley, USA, Jun. 2012
  87. Kuan-Hsien Ho, Xin-Wei Shih, and Jie-Hong R. Jiang, “Clock Rescheduling for Timing Engineering Change Orders,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'12), pages 517-522, Sydney, Australia, Jan. 2012
  88. Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, and Jie-Hong R. Jiang, “Towards Completely Automatic Decoder Synthesis,” Proc. IEEE/ACM Int'l Conf. on Computer Aided Design (ICCAD'11), pages 389-395, San Jose, USA, Nov. 2011
  89. Valeriy Balabanov and Jie-Hong R. Jiang, “Resolution Proofs and Skolem Functions in QBF Evaluation and Applications,” Proc. Int'l Conf. on Computer Aided Verification (CAV'11), pages 149-164, Salt Lake City, Jul. 2011
  90. Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong R. Jiang, Chien-Nan Liu, and Sy-Yen Kuo, “Constraint Generation for Software-Based Post-Silicon Bug Repair with Scalable Resynthesis Technique for Constraint Optimization,” Proc. IEEE Int'l Symp. on Quality Electronic Design (ISQED'11), pages 1-8, Santa Clara, USA, Mar. 2011
  91. Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, and Jie-Hong R. Jiang, “A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques,” Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'10), San Jose, USA, Nov. 2010
  92. Chih-Fan Lai, Jie-Hong R. Jiang, and Kuo-Hua Wang, “Boolean Matching of Function Vectors with Strengthened Learning,” Proc. Int'l Conf. on Computer-Aided Design (ICCAD'10), San Jose, USA, Nov. 2010
  93. Chih-Fan Lai, Jie-Hong R. Jiang, and Kuo-Hua Wang, “BooM: A Decision Procedure for Boolean Matching with Abstraction and Dynamic Learning,” Proc. ACM/IEEE Design Automation Conference (DAC'10), pages 499-504, Anaheim, USA, Jun. 2010
  94. Kuan-Hsien Ho, Jie-Hong R. Jiang, and Yao-Wen Chang, “TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'10), Taipei, Taiwan, Jan. 2010
  95. Jie-Hong R. Jiang, Hsuan-Po Lin, and Wei-Lun Hung, “Interpolating Functions from Large Boolean Relations,” Proc. Int'l Conf. on Computer-Aided Design (ICCAD'09), San Jose, USA, Nov. 2009
  96. Natalia Eliseeva, Jie-Hong R. Jiang, Natalia Kushik, and Nina Yevtushenko, “Symmetrization in Digital Circuit Optimization,” Proc. IEEE East-West Design & Test Symposium (EWDTS'09), Moscow, Russia, Sept. 2009
  97. Jie-Hong R. Jiang, “Quantifier Elimination via Functional Composition,” Proc. Int'l Conf. on Computer Aided Verification (CAV'09), pages 383-397, Grenoble, France, Jun. 2009
  98. Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, and Stephen Jang, “Scalable Don't Care Based Logic Optimization and Resynthesis,” Proc. ACM International Symposium on Field-Programmable Gate Arrays (FPGA'09), pages 151-160, Monterey, California, USA, Feb. 2009
  99. Hsuan-Po Lin, Jie-Hong R. Jiang, and Ruei-Rung Lee, “To SAT or Not to SAT: Ashenhurst Decomposition in a Large Scale,” Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'08), pages 32-37, San Jose, USA, Nov. 2008
  100. Sz-Cheng Huang and Jie-Hong R. Jiang, “A Dynamic Accuracy-Refinement Approach to Timing-Driven Technology Mapping,” Proc. IEEE Int'l Conf. on Computer Design (ICCD'08), pages 538-543, Lake Tahoe, USA, Oct. 2008
  101. Ruei-Rung Lee, Jie-Hong R. Jiang, and Wei-Lun Hung, “Bi-Decomposing Large Boolean Functions via Interpolation and Satisfiability Solving,” Proc. ACM/IEEE Design Automation Conference (DAC'08), pages 636-641, Anaheim, USA, Jun. 2008
  102. Chih-Chun Lee, Jie-Hong R. Jiang, Chung-Yang Huang, and Alan Mishchenko, “Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving,” Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07), pages 227-233, San Jose, USA, Nov. 2007
  103. Jie-Hong R. Jiang and Wei-Lun Hung, “Inductive Equivalence Checking under Retiming and Resynthesis,” Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07), pages 326-333, San Jose, USA, Nov. 2007
  104. Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong R. Jiang, Yao-Wen Chang, “A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits,” Proc. Int'l Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS'07), pages 148-159, Göteborg, Sweden, Sept. 2007
  105. Jie-Hong R. Jiang, “On Some Transformation Invariants under Retiming and Resynthesis,” Proc. Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'05), pages 413-428, Edinburgh, UK, Apr. 2005
  106. Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Tiziano Villa, and Nina Yevtushenko, “Efficient Solution of Language Equations Using Partitioned Representations,” Proc. Design Automation and Test in Europe (DATE'05), pages 418-423, Munich, Germany, Mar. 2005
  107. Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton, “On Breakable Cyclic Definitions,” Proc. IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'04), pages 411-418, San Jose, USA, Nov. 2004
  108. Jie-Hong R. Jiang and Robert K. Brayton, “Functional Dependency for Verification Reduction,” Proc. Int'l Conf. on Computer Aided Verification (CAV'04), pages 268-280, Boston, USA, Jul. 2004

Books:

  1. Supratik Chakraborty, Jie-Hong Roland Jiang, “27th International Conference on Theory and Applications of Satisfiability Testing (SAT 2024),” Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Aug. 2024, ISBN:978-3-95977-334-8

Patents:

  1. Yi-Ting Chung and Jie-Hong R. Jiang, “Functional Timing Analysis Method for Circuit Timing Verification,” 8671375 B1, Aug. 2018

other:

  1. Jie-Hong R. Jiang, Dah-Wei Chiou, and Cheng-En Wu, “Quantum Mechanical Search and Harmonic Perturbation,” Feb. 2007, arXiv e-print quant-ph/0702007.