C-Y Lin, Y-H Wei, and T-C Lee, “A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration,” IEEE Journal of Solid-State Circuits, vol.53 no.5, 1508-1517, May 2018
W-S Chang and T-C Lee, “A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM,” IEEE Transactions on Circuits and Systems, Part I, Nov. 2016
C-Y Lin and T-C Lee, “A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique,” IEEE Transactions on Circuits and Systems, Part I, Jul. 2016
C-Y Lin, C-H Wong, C-H Hsu, Y-H Wei, and T-C Lee, “A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise,” IEEE Transactions on Circuits and Systems, Part II,, Apr. 2016
S-C Wu and T-C Lee, “Ultra-Low Power One-Pin Crystal Oscillator with Self-Charged Technique,” IET Electronic Letters, Apr. 2016
C-L Chang and T-C Lee, “A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor–Sharing Technique for Thermoelectric Energy Harvesting Applications,” Journal of Circuits, Systems and Computers (JCSC), Jan. 2016
P-C Huang, W-S Chang and T-C Lee, “A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise,” IEEE Journal of Solid-State Circuits, vol 49, no. 12, pp. 2964-2975, Dec. 2014
C-C Lee and T-C Lee, “A 2.4-GHz High Efficiency Adaptive Power Harvester,” IEEE Transactions on Very Large Scale Integration Systems, vol 22, no. 2, pp. 434-438, Feb. 2014
C-H Wong and T-C Lee, “A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator,” IEEE Transactions on Circuits and Systems, Part I, vol. 58, no. 3, pp. 1264-1273, May 2013
C-D Su, C-W Lee and T-C Lee, “A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG),” International Journal of Electrical Engineering, Jun. 2012
Y-C Huang and T-C Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques,” IEEE Transactions on Circuits and Systems, Part I, pp. 1157-1166, Jun. 2011
Z-Z Chen and T-C Lee, “The Design and Analysis of Dual-Delay-Path Ring Oscillators,” IEEE Transactions on Circuits and Systems, Part I, pp. 470-478, Mar. 2011
Z-Z Chen and T-C Lee, “The Study of a Dual-Mode Ring Oscillator,” IEEE Transactions on Circuits and Systems, Part II, pp. 210-214, 2011
T-C Lee and C-H Lin, “Nonlinear R-2R Transistor-Only DAC,” IEEE Transactions on Circuits and Systems, Part I, Nov. 2010
K-T Chen and T-C Lee, “A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB,” International Journal of Electrical Engineering, Jun. 2010
Yen-Chuan Huang and Tai-Cheng Lee, “A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology,” IEEE Journal of Solid-State Circuits, Mar. 2010
Li-Han Hung; Tai-Cheng Lee, “A Split-Based Digital Background Calibration Technique in Pipelined ADCs,” IEEE Transactions on Circuits and Systems, Part II, Nov. 2009
K-J Hsian and Tai-Cheng Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation,” IEEE Journal of Solid-State Circuits, Sept. 2009
Zuow-Zun Chen and Tai-Cheng Lee, “A Multiphase Compensation Method with Dynamic Element Matching Technique in S-D Fractional-N Frequency Synthesizers,” Journal of Semiconductor Technology and Science, Sept. 2008
K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning,” IEEE Journal of Solid-State Circuits, Jun. 2008
D.-L. Shen and T.-C. Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers,” IEEE Journal of Solid-State Circuits, Feb. 2007
T.-C. Lee and Y.-C. Huang, “The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application,” IEEE Journal of Solid-State Circuits, Jun. 2006
T.-C. Lee and K.-J. Hsiao, “The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application,” IEEE Journal of Solid-State Circuits, Jun. 2006
T.-C. Lee and C.-C. Chen, “A Mixed-Signal GFSK Demodulator for Bluetooth,” IEEE Transactions on Circuits and Systems Part II, Mar. 2006
T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, Jun. 2003
T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire,” IEEE Journal of Solid-State Circuits, Mar. 2001
Conference & proceeding papers:
T-C Lee and D-N Jhou, “A 5-GHz Chirp Frequency Synthesizer with a Low 1/f Noise LC Oscillator,” PIERS 2018, Toyama, Jul. 2018
W-S Chang, D-N Jhou, Y-H Yang and T-C Lee, “An Energy-Efficient Self-Charged Crystal Oscillator with a Quadrature-Phase Shifter Technique,” IEEE Asian Solid-State Circuit Conference, Dec. 2017
J-C Hsiao and T-C Lee, “A 10-Gb/s Equalizer with Digital Adaptation,” International SoC Design Conference, Nov. 2017
D-N Jhou, W-S Chang, and T-C Lee, “A 5.12-GHz Fractional-N clock multiplier with an LC-VCO-based MDLL,” IEEE Symposium on VLSI Circuits, Jun. 2017
C-P Wang and T-C Lee, “ Technique for In-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers,” IEEE Asian Solid-State Circuit Conference, Nov. 2016
C-L Chang and T-C Lee, “An thermoelectric and RF multi-source energy harvesting system,” 2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG), Jul. 2016
B-C Lin,W-S Chang and T-C Lee, “A 2X25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology,” IEEE VLSI-DAT, Apr. 2016
C-Y Lin, Y-H Wei, and T-C Lee, “A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration,” International Solid-State Circuits Conference, Feb. 2016
C-K Hsu and T-C Lee, “A Single-Channel 10-b 400-MS/s 8.7-mW Pipeline ADC in a 90-nm Technology,” IEEE Asian Solid-State Circuit Conference, Nov. 2015
T-Y Wang and T-C Lee, “An 84.7-DR Wide BW Incremental ADC,” IEEE VLSI-DAT, Apr. 2015
C-L Chang and T-C Lee, “A Compact Multi-Input Thermoelectric Energy Harvesting System with 58.5% Power Conversion Efficiency and 32.4-mW Output Power Capability,” International Symposium on Integrated Circuits, Dec. 2014
L-H Chiueh and T-C Lee, “A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits,” IEEE Asian Solid-State Circuit Conference, Nov. 2014
Y-H Kang, C-Y Lin and T-C Lee, “ A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator,” IEEE ISCAS, Jun. 2014
C-Y Lin and T-C Lee, “A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique,” IEEE Symposium on VLSI Circuits, Jun. 2014
J-A Cheng, W-S Chang and T-C Lee, “A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth,” IEEE VLSI-DAT, Apr. 2014
P-C Huang, W-S Chang and T-C Lee, “A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise,” International Solid-State Circuit Conference, San Francisco, Feb. 2014
C-Y Lin and T-C Lee, “Jitter Error Cancellation Technique in Digital Domain for ADC,” IEEE VLSI-DAT, Apr. 2013
C-Y Lin Y-C Huang and T-C Lee, “Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies,” IEEE VLSI-DAT, Apr. 2013
C-C Ho and T-C Lee, “A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter,” IEEE VLSI DAT, Apr. 2012
Y-C Huang, C-Y Lin and T-C Lee, “A 10-b 400Ms/s 36mW interleaved ADC,” IEEE RFIT Symposium, Dec. 2011
P Zhang, T-C Lee, “Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS,” International Conference on Sampling Theory and Applications, May 2011
K Fong, Z-Z Chen and T-C Le, “An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay,” IEEE Asian Pacific Conference on Circuits and Systems, Dec. 2010
Y-C Hung, K Fong and T-C Lee, “A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay,” IEEE Asian Solid-State Circuit Conference, Nov. 2010
C-Y Lin, C-Y Chiang and T-C Lee, “An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III,” IEEE Custom Integrated Circuits Conference, Sept. 2010
Yen-Chuang Huang and Tai-Cheng Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques,” International Solid-State Circuit Conference, San Francisco, Feb. 2010
Feng-Chiu Hsieh and Tai-Cheng, “A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification,” IEEE Asian Solid-State Circuit Conference, Fukuoka, Japan, Nov. 2008
Shih-Chun Lin and Tai-Cheng Lee, “An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits,” IEEE Aisan Solid-State Circuit Conference, Fukuoka, Japan, Nov. 2008
K-J Hsiao, M-H Lee and T-C Lee, “ A CLOCK AND DATA RECOVERY CIRCUIT WITHWIDE LINEAR RANGE FREQUENCY,” IEEE VLSI-DAT, Apr. 2008
Y-C Huang, Q-T Chen and T-C Lee, “A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections,” IEEE VLSI-DAT, Apr. 2008
K-J Hsiao and T.-C. Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation,” IEEE International Solid-State Circuit Conference, Feb. 2008
D.-L Shen, Y-C Lai and T.-C. Lee, “A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration,” IEEE Asian Solid-State Circuit Conference, Nov. 2007
K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning,” Symposium on VLSI Circuits, Jun. 2007
G-J Chen, H-H Chiu and T-C Lee, “A 4-Channel Poly-Phase Filter for Cognitive Radio Systems,” IEEE VLSI-DAT, Apr. 2007
H-S Kao, M-J Yang, T-C Lee, “A Delay-Line-Based GFSK Demodulator for Low-IF Receivers,” International Solid-State Circuit Conference (ISSCC), Feb. 2007
Q.-T. Chen, Y.-C. Huang and T.-C. Lee, “A 14Gb/s 4PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections,” Asian Solid-State Circuit Conference (ASSCC), Nov. 2006
D-L Shen and T-C Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-loop Amplifiers,” IEEE Symposium on VLSI Circuits, Jun. 2006
Y-M Liao and T-C Lee, “A 6-b 1.3Gs/s A/D Converter with C-2C Switch–Capacitor Technique,” IEEE VLSI-DAT, Apr. 2006
T.-C. Lee and W.-L. Lee, “ A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2006
T.-C. Lee and etal, “A 40-GHz Distributed-Load Static Divider,” IEEE Asian Solid-State Circuit Conference, Nov. 2005
T. C. Lee and K-J Hsiao, “A DLL-Based Frequency Multiplier For MBOA-UWB System,” IEEE Symposium on VLSI Circuits, Jun. 2005
T. C. Lee and Y. C. Huang, “A Miller Divider Based Clock Generator for MBOA-UWB Application,” IEEE Symposium on VLSI Circuits, Jun. 2005
D. L. Shen and T. C. Lee, “A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs,” ISCAS, May 2005
T. C. Lee and Y. C. Huang, “An Optimization Technique for RF Buffers with Active Inductors,” ISCAS, May 2005
Y. H. Chen, and T. C. Lee, “ 6 bits 500-Ms/s Digital Self-Calibrated Pipelined Analog-to-Digital Converter,” AP-ASIC, pp98-101, Aug. 2004
H. C. Wang, H. S. Kao, and T. C. Lee, “An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC,” AP-ASIC, pp. 102-105, Aug. 2004
T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE VLSI Circuits Symposium, Kyoto, Japan, Jun. 2001
T. C. Lee and B. Razavi, “A 125-MHz Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire,” IEEE Custom Integrated Circuits Conference, San Diego, May 2001
T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire,” IEEE Custom Integrated Circuits Conference, Orlando, May 2000
5. Y-H Wei, C-Y Lin, and T-C Lee, “A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration,” IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Books:
T. C. Lee, “High-Speed CMOS Circuits for Gigabit Ethernet,” Ph.D. dissertation, UCLA, 2001
Patents:
T-C Lee, C-Y Lin and Y-H Wei, “Analog-to-digital converting system and converting method,” US 9,685,970, Jul. 2016
T-C Lee and C-W Wong, “Circuit for spread spectrum transmission and method thereof,” US 8,787,424, Jul. 2014
Y-C Huang and T-C Lee, “Pipelined analog-to-digital converter and method for converting analog signal to digital signal,,” US 8,471,753, Jun. 2013
T-C Lee and C-H Lin, “Digital-to-analog converter (DAC) and an associated method,” US Patent 7982650, Jun. 2011
L-H Hung and T-C Lee, “Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus,” US 7932849, Apr. 2011
T-C Lee and B. Razavi, “A Stabilization technique for phase-locked frequency synthesizers,” US 6864753, Mar. 2005