劉深淵特聘教授的著作列表 - Publication List of Shen-Iuan Liu

Publication List of 劉深淵 Shen-Iuan Liu

Journal articles & book chapters:

  1. Ting-Kuei Kuan and Shen-Iuan Liu, “A loop gain optimization technique for integer-N TDC-based phase-locked loops,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 62, pp. 1873-1882, Jul. 2015
  2. Chih-Lu Wei, Ting-Kuei Kuan and Shen-Iuan Liu, “A sub-harmonically injection-locked PLL with calibrated injection pulse width,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, pp. 548-552, Jun. 2015
  3. Yu-Hsun Chien, Kuan-Lin Fu and Shen-Iuan Liu, “A 3-25 Gb/s 4-channel receiver with noise-canceling TIA and power scalable LA,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 845-849, Nov. 2014
  4. I-Ting Lee, Shih-Han Ku and Shen-Iuan Liu, “An all-digital de-spreading clock generator,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 16-20, Jan. 2014
  5. Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li and Shen-Iuan Liu, “Ultrasonic Power/Data Telemetry and Neural Stimulator with OOK-PM Signaling,” IEEE Trans. Circuits and Systems-II: Express Briefs,, vol. 60,, pp. 827-831, Dec. 2013
  6. I-Ting Lee, Shih-Han Ku, and Shen-Iuan Liu, “An all-digital spread-spectrum clock generator with self-calibrated bandwidth,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 60, pp. 2813-2822, Nov. 2013
  7. Shih-Yuan Kao and Shen-Iuan Liu, “A 10-Gb/s adaptive parallel receiver with joint XTC and DFE using power detection,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 2815-2826, Nov. 2013
  8. Pin-Hao Feng and Shen-Iuan Liu, “A 300GHz divide-by-2 CMOS ILFD using frequency boosting technique,” IEEE Microwave and Wireless Components Letters, vol. 23, pp. 599-601, Nov. 2013
  9. Yan-Yu Lin and Shen-Iuan Liu, “4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 622-626, Oct. 2013
  10. I-Ting Lee, Kai-Hui Zeng, and Shen-Iuan Liu, “A 4.8GHz divider-less sub-harmonically injection-locked all-digital PLL with FOM of -252.5dB,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 547-551, Sept. 2013
  11. Yan-Yu Lin and Shen-Iuan Liu, “4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 252-256, May 2013
  12. Pin-Hao Feng and Shen-Iuan Liu, “A current-reused injection-locked frequency multiplication/division circuit in 40-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, pp. 1523-1532, Apr. 2013
  13. Pin-Hao Feng and Shen-Iuan Liu, “Divide-by-three injection-locked frequency dividers over 200GHz in 40-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 405-416, Feb. 2013
  14. Shih-Yuan Kao and Shen-Iuan Liu, “A 7.5-Gb/s one-tap FFE transmitter with adaptive far-end crosstalk cancellation using duty cycle detection,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 391-404, Feb. 2013
  15. Yi-Chieh Huang and Shen-Iuan Liu, “A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing,” IEEE Journal of Solid-State Circuits, vol. 48, pp. 417-428, Feb. 2013
  16. I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, “A wide-range PLL using self-healing prescaler/VCO in 65-nm CMOS,” IEEE Trans. on VLSI Systems, vol. 21, pp. 250-258, Feb. 2013
  17. I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, “A leakage-current-recycling phase-locked loop in 65nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 47, pp. 2693-2700, Nov. 2012
  18. I-Ting Lee, Chiao-Hsing Wang, Ju-Rong Sha, Ying-Zong Juang, and Shen-Iuan Liu, “A D-band divide-by-3 injection-locked frequency divider in 65nm CMOS,” IET Electronics Letters, vol. 48, pp. 1041-1042, Sept. 2012
  19. I-Ting Lee, Hung-Yu Lu, and Shen-Iuan Liu, “ A 6GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering technique,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 59, pp. 267-271, May 2012
  20. I-Ting Lee, Chiao-Hsing Wang, Chun-Lin Ko, Ying-Zong Juang, and Shen-Iuan Liu, “A 3.6mW 125.7~131.86GHz divide-by-4 injection-locked frequency divider in 90nm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 22, pp. 132-134, Mar. 2012
  21. Yi-Chieh Huang, Ping-Ying Wang, and Shen-Iuan Liu, “An all-digital jitter-tolerance measurement technique for CDR circuits,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 59, pp. 148-152, Mar. 2012
  22. Ke-Hou Chen, and Shen-Iuan Liu, “Inductorless wideband CMOS low-noise amplifiers using noise-canceling technique,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 59, pp. 305-314, Feb. 2012
  23. I-Ting Lee, and Shen-Iuan Liu, “G-Band injection-locked frequency dividers using π-type LC Network,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 59, pp. 315-323, Feb. 2012
  24. Kun-Hung Tsai, and Shen-Iuan Liu, “A 104GHz phase-locked loop using a VCO at second pole frequency,” IEEE Trans. on VLSI Systems, vol. 20, pp. 80-88, Jan. 2012
  25. Chang-Lin Hsieh, and Shen-Iuan Liu, “Decision feedback equalizers using back-gate feedback technique,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 897-901, Dec. 2011
  26. Bo-Yu Lin, and Shen-Iuan Liu, “A 132.6GHz phase-locked loop in 65nm digital CMOS,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 617-621, Oct. 2011
  27. I-Ting Lee,Chiao-Hsing Wang, and Shen-Iuan Liu, “A current-reused divide-by-3 injection-locked frequency divider in 65nm CMOS,” IET Electronics Letters, vol. 47, pp. 1029-1030, Sept. 2011
  28. Bo-Yu Lin, and Shen-Iuan Liu, “A 113.92~118.08GHz injection-locked frequency divider with triple-split-inductor technique,” IEEE Microwave and Wireless Components Letters, vol. 21, pp. 436-438, Aug. 2011
  29. Wei-Jen Huang, Shigeisa Nagayasu, and Shen-Iuan Liu, “A rail-to-rail class-B buffer with DC level-shifting current mirror and distributed Miller compensation for LCD column drivers,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 58, pp. 1761-1772, Aug. 2011
  30. Chang-Lin Hsieh, and Shen-Iuan Liu, “A 1~16Gb/s wide-range clock/data recovery circuit with bidirectional frequency detector,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 487-491, Aug. 2011
  31. Bo-Yu Lin, and Shen-Iuan Liu, “Analysis and design of D-band injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, vol. 46, pp.1250-1264, Jun. 2011
  32. Chao-Ching Hung, and Shen-Iuan Liu, “A 40GHz fast-locked all-digital phase-locked loop using modified bang-bang algorithm,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp.321-325, Jun. 2011
  33. Shih-Yuan Kao and Shen-Iuan Liu, “A digitally-calibrated phase-locked loop with supply sensitivity suppression,” IEEE Trans. on VLSI Systems, vol. 19, pp.592-602, Apr. 2011
  34. Chao-Ching Hung, and Shen-Iuan Liu, “A noise-filtering technique for fractional-N frequency synthesizers,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 58, pp. 139-143, Mar. 2011
  35. Wei-Jen Huang and Shen-Iuan Liu, “A PSRR-enhanced low-dropout regulator,” IET Electronics Letters, vol. 47, pp. 17-18, Jan. 2011
  36. I-Ting Lee, Chiao-Hsing Wang, Bo-Yu Lin, and Shen-Iuan Liu, “A 258.16~259.95 GHz injection-locked frequency divider,” IET Electronics Letters, vol. 46, pp. 1438-1439, Oct. 2010
  37. Jung-Yu Chang, and Shen-Iuan Liu, “A phase-locked loop with background leakage current compensation,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 57, pp. 666-670, Sept. 2010
  38. Shih-Yuan Kao and Shen-Iuan Liu, “A 20Gbps transmitter with adaptive pre-emphasis in 65nm CMOS technology,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 57, pp. 319-323, May 2010
  39. Shih-Yuan Kao and Shen-Iuan Liu, “A 1.62/2.7Gbps adaptive transmitter with 2-tap pre-emphasis using a propagation-time detector,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 57, pp. 178-182, Mar. 2010
  40. Jian-Hao Lu and Shen-Iuan Liu, “A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 433-446, Feb. 2010
  41. Mu-Chen Huang and Shen-Iuan Liu, “A 10MS/s to 100kS/s power-scalable fully-differential CBSC 10-bit pipelined ADC with adaptive biasing,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 57, pp. 11-15, Jan. 2010
  42. Jung-Yu Chang, and Shen-Iuan Liu, “ A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS,” IET Circuits, Devices & Systems, vol.3, pp. 350-358, Dec. 2009
  43. Sheng-You Lin, and Shen-Iuan Liu, “A 1.5GHz all-digital spread spectrum clock generator,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 3111-3119, Nov. 2009
  44. Chi-Nan Chuang, and Shen-Iuan Liu, “A 20MHz~3GHz wide-range multi-phase delay-locked loop,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 56, pp. 850-854, Nov. 2009
  45. Jian-Hao Lu, and Shen-Iuan Liu, “A 50Gb/s 10mW analog equalizer using transformer feedback technique in 65nm CMOS technology,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 56, pp. 783-787, Oct. 2009
  46. Chao-Ching Hung, and Shen-Iuan Liu, “A leakage-compensated PLL in 65nm CMOS technology,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp.525-529, Jul. 2009
  47. I-Hsin Wang, Hwei-Yu Lee, and Shen-Iuan Liu, “ An 8-bit 20MS/s ZCBC time-domain analog-to-digital data converter,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 545-549, Jul. 2009
  48. I-Ting Lee, Kun-Hung Tsai, and Shen-Iuan Liu, “A 104~112.8GHz CMOS injection-locked frequency divider,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 555-559, Jul. 2009
  49. Mu-Chen Huang, and Shen-Iuan Liu, “A fully-differential comparator-based switched-capacitor delta-sigma modulator,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 56, pp. 369-373, May 2009
  50. Lan-Chou Cho, Chihun Lee, Chao-Ching Hung and Shen-Iuan Liu, “A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 775-783, Mar. 2009
  51. Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, and Chun-Ting Liu, “A phase-locked loop with self-calibrated charge pumps in 3µm LTPS-TFT Technology,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 56, pp. 142-146, Feb. 2009
  52. Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, and Shen-Iuan Liu, “A single-PLL UWB frequency synthesizer using multiphase coupled ring oscillator and current-reused multiplier,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 56, pp. 107-111, Feb. 2009
  53. Jian-Hao Lu, Ke-Hou Chen, and Shen-Iuan Liu, “A 10Gb/s inductorless CMOS analog equalizer with interleaved active feedback topology,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 56, pp. 97-101, Feb. 2009
  54. Shao-Hung Lin, and Shen-Iuan Liu, “Bang-bang phase/frequency detectors for unilateral continuous-rate CDR circuits,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 55, pp. 1214-1217, Dec. 2008
  55. Chao-Chyun Chen, and Shen-Iuan Liu, “An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 2413-2421, Nov. 2008
  56. Chih-Fan Liao, and Shen-Iuan Liu, “A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 2492-2502, Nov. 2008
  57. Shao-Ku Kao, and Shen-Iuan Liu, “A delay-locked loop with statistical background calibration,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 55, pp.961-965, Oct. 2008
  58. Che-Fu Liang, Hong-Lin Chu, and Shen-Iuan Liu, “10Gbps inductorless CDRs with digital frequency calibration,” IEEE Trans. Circuits and Systems-I: Regular Papers, pp. 2514-2524, pp. 2514-2524, Oct. 2008
  59. Chi-Nan Chuang, and Shen-Iuan Liu, “A 3~8GHz delay-locked loop with cycle jitter calibration,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 55, pp. 1094-1098, Oct. 2008
  60. Lan-Chou Cho, Kun-Hung Tsai, Chao-Ching Hung, and Shen-Iuan Liu, “A 81.5~85.9GHz injection-locked frequency divider in 65nm CMOS,” IET Electronics Letters, pp. 966-968, pp. 966-968, Jul. 2008
  61. Wei-Jen Huang, and Shen-Iuan Liu, “Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array,” IET Circuits, Devices & Systems, vol. 2, pp. 306-316, Jun. 2008
  62. Chihun Lee, Lan-Chou Cho, Jia-Hao Wu and Shen-Iuan Liu, “A 50.8-53GHz clock generator using a harmonic-locked PD in 0.13um CMOS,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 55, pp. 404-408, May 2008
  63. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, “A jitter-tolerance-enhanced CDR using a GDCO-based phase detector,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 1217-1226, May 2008
  64. Chih-Fan Liao and Shen-Iuan Liu, “40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 642-655, Mar. 2008
  65. I-Hsin Wang, and Shen-Iuan Liu, “A 0.18μm CMOS 1.25Gbps automatic gain control amplifier,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 55, pp. 136-140, Feb. 2008
  66. Chuan-Kang Liang, Rong-Jyi Yang, and Shen-Iuan Liu, “An all-digital fast-locking programmable DLL-based clock generator,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 55, pp. 361-369, Feb. 2008
  67. Che-Fu Liang, Shin-Hua Chen, and Shen-Iuan Liu, “A digital calibration technique for charge pumps in phase-locked systems,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 390-398, Feb. 2008
  68. Chao-Chyun Chen, Jung-Yu Chang, and Shen-Iuan Liu, “A DLL-based variable-phase clock buffer,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 1702-1706, Dec. 2007
  69. Rong-Jyi Yang and Shen-Iuan Liu, “A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology,” IEEE Journal of Solid-State Circuits, SC-42, pp. 2338-2347, Nov. 2007
  70. Chi-Nan Chuang, and Shen-Iuan Liu, “A 0.5~5GHz wide-range multi-phase DLL with a calibrated charge pump,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 939-943, Nov. 2007
  71. Ding-Shiuan Shen and Shen-Iuan Liu, “A low-jitter spread spectrum clock generator using FDMP,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 979-983, Nov. 2007
  72. Che-Fu Liang, Hsin-Hua Chen, and Shen-Iuan Liu, “Spur-suppression techniques for frequency synthesizers,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 653-657, Aug. 2007
  73. Chein-Lung Chen , Ke-Hou Chen, and Shen-Iuan Liu, “Efficiency-enhanced CMOS rectifier for wireless telemetry,” IET Electronics Lettters, vol. 43, pp. 976-978, Aug. 2007
  74. Shao-Ku Kao, Bo-Jiun Chen, and Shen-Iuan Liu, “A 62.5-625MHz anti-reset all-digital delay-locked loop,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 566-570, Jul. 2007
  75. Chein-Lung Chen , Wei-Jen Huang, and Shen-Iuan Liu, “A CMOS low dropout regulator with dynamic zero compensation,” IET Electronics Lettters, vol. 43, pp. 751-752, Jul. 2007
  76. Chao-Chyun Chen, Sheng-Chou Lee and Shen-Iuan Liu, “A capacitor multiplication technique using a second-generation current conveyor in the loop filter of the phase-locked loops,” International Journal of Electrical Engineering, vol. 14, pp.239-245, Jun. 2007
  77. Lan-Chou Cho, Chihun Lee, and Shen-Iuan Liu, “A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology,” IEEE Journal of Solid-State Circuits, SC-42, pp.1261-1270, Jun. 2007
  78. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, “A multi-band burst-mode clock and data recovery circuit,” IEICE Trans. on Electronics, vol. E90-C, pp. 802-810, Apr. 2007
  79. Ke-Hou Chen, Jian-Hao Lu, Bo-Jiun Chen and Shen-Iuan Liu, “An ultra-wideband 0.4-10GHz LNA in 0.18um CMOS,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 217-221, Mar. 2007
  80. I-Hsin Wang and Shen-Iuan Liu, “A CMOS 5-bit 5GSample/sec analog-to-digital converter in 0.13um CMOS,” Journal of Semiconductor Technology and Science, pp. 28-35, Mar. 2007
  81. Chih-Fan Liao and Shen-Iuan Liu, “A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receivers,” IEEE Journal of Solid-State Circuits, SC-42, pp. 329-339, Feb. 2007
  82. Rong-Jyi Yang and Shen-Iuan Liu, “A 40~550MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm,” IEEE Journal of Solid-State Circuits, SC-42, pp. 361-373, Feb. 2007
  83. Sung-Rung Han, Chi-Nan Chuang, and Shen-Iuan Liu, “A time-constant calibrated phase-locked loop with a fast-locked time,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 54, pp. 34-37, Jan. 2007
  84. Shao-Ku Kao and Shen-Iuan Liu, “All-digital fast-locked synchronous duty cycle corrector,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol.53, pp. 1363-1367, Dec. 2006
  85. Che-Fu Liang, Shih-Tsai Liu and Shen-Iuan Liu, “A calibrated pulse generator for impulse-radio UWB applications,” IEEE Journal of Solid-State Circuits, SC-41, pp. 2401-2407, Nov. 2006
  86. Wei-Jen Huang and Shen-Iuan Liu, “A sub-1V capacitor-free low-dropout regulator,” IEE Electronics Lettters, vol. 43, pp. 1395-1396, Nov. 2006
  87. Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang and Shen-Iuan Liu, “A 155.52Mbps ~ 3.125Gbps continuous-rate clock and data recovery circuit,” IEEE Journal of Solid-State Circuits, SC-41, pp. 1380-1390, Jun. 2006
  88. You-Jen Wang, Shao-Ku Kao and Shen-Iuan Liu, “All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles,” IEEE Journal of Solid-State Circuits, SC-41, pp. 1262-1274, Jun. 2006
  89. Chien-Hung Kuo, Shr-Lung Chen, and Shen-Iuan Liu, “A magnetic field to digital converter using PWM and TDC techniques,” IEE Proceedings of Circuits, Devices and Systems, vol. 153, pp. 247- 252, Jun. 2006
  90. Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo and Shen-Iuan Liu, “A 0.7-2GHz self-calibrated multiphase delay-locked loop,” IEEE Journal of Solid-State Circuits, SC-41, pp.1051-1061, May 2006
  91. I-Hsin Wang, Jia-Liang Lin and Shen-Iuan Liu, “A 5bit, 10Gsamples/sec track-and-hold circuit with input feedthrough cancellation,” IEE Electronics Letters, vol. 42,, pp. 457-458, Apr. 2006
  92. Rong-Jyi Yang, Kuan-Hua Chao and Shen-Iuan Liu, “A 200Mbps~2Gbps continuous-rate clock and data recovery circuit,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 53, pp. 842-847, Apr. 2006
  93. Chun-Yi Kuo, Jung-Yu Chang, and Shen-Iuan Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 53, pp. 526-533, Mar. 2006
  94. Chi-Nan Chuang and Shen-Iuan Liu, “A 1V phase locked loop with leakage compensation in 0.13um CMOS technology,” IEICE Trans. on Electronics, vol. E89-C, pp. 295-299, Mar. 2006
  95. Wei-Jen Huang, Sao-Hung Lu and Shen-Iuan Liu, “CMOS low dropout linear regulator with single Miller capacitor,” IEE Electronics Letters, vol. 42, pp. 216- 217, Feb. 2006
  96. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, “CMOS differential-mode exponential voltage-to-current converters,” Journal of Analog Integrated Circuits and Signal Processings, vol. 45, pp. 163-168, Nov. 2005
  97. Chia-Hsin Wu, Chun-Yi Kuo, and Shen-Iuan Liu, “Selective metal parallel shunting inductor and its VCO application,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 52, pp. 1811-1818, Sept. 2005
  98. Rong-Jyi Yang and Shen-Iuan Liu, “A fully integrated 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector,” IEICE Trans. on Electronics, vol.E88-C, pp. 1726-1730, Aug. 2005
  99. Rong-Jyi Yang and Shen-Iuan Liu, “A wide-range multiphase delay-locked loop using mixed-mode VCDLs,” IEICE Trans. on Electronics, vol. E88-C, pp. 1248-1252, Jun. 2005
  100. Sung-Rung Han and Shen-Iuan Liu, “A single-path pulsewidth control loop with a built-in delay-locked loop,” IEEE Journal of Solid-State Circuits, SC-40, pp. 1130-1135, May 2005
  101. Hsiang-Hui Chang and Shen-Iuan Liu, “A wide-range and fast-locking all-digital cycle-controlled delay-locked loop,” IEEE Journal of Solid-State Circuits, SC-40, pp. 661-670, Mar. 2005
  102. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, “CMOS current-mode divider and its applications,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol. 52, pp. 145-148, Mar. 2005
  103. Chia-Hsin Wu, Wei-Sheng Chen, Chih-Hun Lee, and Shen-Iuan Liu, “CMOS wide-band amplifiers using multiple inductive-series peaking technique,” IEEE Journal of Solid-State Circuits, SC-40, pp. 548-552, Feb. 2005
  104. Ming-Huang Liu, Wei-Yang Ou, Tsung-Yi Su, Kuo-Chan Huang and Shen-Iuan Liu, “A 1.5V 12-bit 16MS/s pipelined CMOS ADC with 68dB dynamic range,” Journal of Analog Integrated Circuits and Signal Processings, vol. 41, pp. 269-278, Dec. 2004
  105. Guo-Ming Sung and Shen-Iuan Liu, “Error correction of transformed rectangular model of concave and convex MAGFETs with AC bias,” IEE Proceedings of Circuits, Devices and Systems, vol. 151, pp. 593-600, Dec. 2004
  106. Chien-Hung Kuo and Shen-Iuan Liu, “A 1V 10.7MHz fourth-order bandpass DS modulators using two switched-opamps,” IEEE Journal of Solid-State Circuits, SC-39, pp. 2041-2045, Nov. 2004
  107. Hsiang-Hui Chang, Rong-Jyi Yang, and Shen-Iuan Liu, “Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 51, pp. 2356- 2364, Nov. 2004
  108. Rong-Jyi Yang, Shang-Ping Chen, and Shen-Iuan Liu, “A 3.125Gbps Clock and Data Recovery Circuit for the 10Gbase-LX4 Ethernet,” IEEE Journal of Solid-State Circuits, SC-39, pp. 1356-1560, Aug. 2004
  109. Weihsing Liu and Shen-Iuan Liu, “Low-voltage and low-power CMOS voltage-to-current converter,” IEICE Trans. on Electronics, vol. E87-C, pp. 1029-1033, Jun. 2004
  110. Ming-Huang Liu, Wei-Yang Ou, Tsung-Yi Su, Kuo-Chan Huang and Shen-Iuan Liu, “A low-voltage low-power 13-bit 16MSPS CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, SC-39, pp. 834-836, May 2004
  111. Chien-Hung Kuo, Shr-Lung Chen and Shen-Iuan Liu, “Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators,” IEEE Sensors Journal, vol. 4, pp. 226- 231, Apr. 2004
  112. Chih-Hao Sun and Shen-Iuan Liu, “A Mixed-mode Synchronous Mirror Delay Insensitive to Supply and Load Variations,” Journal of Analog Integrated Circuits and Signal Processings, vol. 39, pp. 75-80, Apr. 2004
  113. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei, “Low voltage and low power CMOS exponential-control variable-gain amplifier,” IEICE Trans. on Fundamentals of Electronics. Communications and Computer Sciences, vol. E87-A, pp. 952-954, Apr. 2004
  114. Weihsing Liu, Shen-Iuan Liu and Shui-Ken We, “CMOS exponential-control variable-gain amplifiers,” IEE Proceedings of Circuits, Devices and Systems, vol. 151, pp. 83-86, Apr. 2004
  115. Sung-Rung Han and Shen-Iuan Liu, “A 500MHz~1.25GHz fast-locking pulsewidth control loop with presettable duty cycle,” IEEE Journal of Solid-State Circuits, SC-39, pp. 463-468, Mar. 2004
  116. Weihsing Liu and Shen-Iuan Liu, “Low-voltage CMOS voltage-mode divider and its application,” IEICE Trans. on Electronics, vol. E87-A, pp. 330-334, Feb. 2004
  117. Hsiang-Hui Chang, Chien-Hung Kuo, Ming-Huang Liu, and Shen-Iuan Liu, “A sub-1V fourth-order bandpass delta-sigma modulator,” Journal of Analog Integrated Circuits and Signal Processings, vol. 37, pp. 179-189,, Dec. 2003
  118. Chia-Hsin Wu, Chih-Chun Tang, Kun-Hsien Li and Shen-Iuan Liu, “CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90 delay network,” IEE Proceedings of Circuits, Devices and Systems, vol. 150, pp. 439-444, Oct. 2003
  119. Weihsing Liu and Shen-Iuan Liu, “CMOS Tunable 1/x Circuit and its Applications,” IEICE Trans. on Fundamentals, vol. E-86A, pp. 1896-1899, Jul. 2003
  120. Hsiang-Hui Chang, Giang-Kaai Dehng and Shen-Iuan Liu, “An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus,” Bulletin of the College of Engineering, National Taiwan University, no. 88, pp. 87-96, Jun. 2003
  121. Chia-Hsin Wu, Chih-Chun Tang, and Shen-Iuan Liu, “Analysis of on-chip spiral inductors using the distributed capacitance model,” IEEE Journal of Solid-State Circuits, SC-38, pp. 1040-1044, Jun. 2003
  122. Shr-Lung Chen, Chien-Hung Kuo and Shen-Iuan Liu, “CMOS magnetic field to frequency converter,” IEEE Sensors Journal, vol. 3, pp. 241-245, Apr. 2003
  123. Hsiang-Hui Chang, I-Hui Hua and Shen-Iuan Liu, “A Spread Spectrum Clock Generator with Triangular Modulation,” IEEE Journal of Solid-State Circuits, SC-38, pp. 673-676, Apr. 2003
  124. Hsiang-Hui Chang, Jyh-Woei Lin, and Shen-Iuan Liu, “A fast locking and low jitter delay-locked loop using DHDL,” IEEE Journal of Solid-State Circuits, SC-38, pp. 343-346, Feb. 2003
  125. Weihsing Liu and Shen-Iuan Liu, “CMOS exponential function generator,” Electronics Letters, vol. 39, pp. 1-2, Jan. 2003
  126. Chien-Hung Kuo, Tzu-Chien Hsueh, and Shen-Iuan Liu, “Multi-bit delta-sigma modulator using a modified DWA algorithm,” Journal of Analog Integrated Circuits and Signal Processings, pp. 289-300, Nov. 2002
  127. Chih-Chun Tang and Shen-Iuan Liu, “A 1V 5.8GHz low noise amplifier in a 0.35um standard CMOS process,” Journal of the Chineses Institute of Electrical Engineering, Series E, vol. 9, No. 4, pp. 395-400, Nov. 2002
  128. Yuh-Shyan Hwang, Pei-Tzu Hung, Wei Chen, Shen-Iuan Liu, “Systematic generation of current-mode linear transformation filters based on multiple output CCIIs,” Journal of Analog Integrated Circuits and Signal Processings, pp. 123-134, Aug. 2002
  129. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE Journal of Solid-State Circuits, SC-37, pp. 1021-1027, Aug. 2002
  130. Chih-Chun Tang, Kun-Hsien Li, and Shen-Iuan Liu, “2.4GHz offset-canceling down-conversion mixer,” Electronics Letters, vol. 38, pp. 395-396, Apr. 2002
  131. Chih-Chun Tang, Chia-Hsin Wu, and Shen-Iuan Liu, “Miniature 3D inductors in standard CMOS process,” IEEE Journal of Solid-State Circuits, vol. 37, pp.471-480, Apr. 2002
  132. Jiann-Jong Chen, Hen-Wai Tsao and Shen-Iuan Liu, “Voltage-mode MOSFET-C filters using operational transresistance amplifiers (OTRAs) with reduced parasitic capacitance effect,” accepted by IEE Proceedings-Circuits Devices and Systems, vol. 148, pp. 242-249, Oct. 2001
  133. Chien-Hung Kuo, Shr-Lung Chen, Lee-An Ho and Shen-Iuan Liu, “CMOS oversampling magnetic to digital converters,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1582-1586, Oct. 2001
  134. Giang-Kaai Dehng, Jyh-Woei Lin and Shen-Iuan Liu, “A fast-lock mixed-mode DLL Using a 2-b SAR Algorithm,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1464-1471, Sept. 2001
  135. Wei-Hung Chen, Giang-Kaai Dehng, Jong-Woei Chen and Shen-Iuan Liu, “A 400MHz serial link for AS-memeory systems using a PWM scheme,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1498-1505, Sept. 2001
  136. June-Ming Hsu,Guang-Kaai Dehng, Ching-Yuan Yang, Chu-Yuan Yang and Shen-Iuan Liu, “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, pp. 826-834, Sept. 2001
  137. Chih-Chun Tang, Chia-Hsin Wu, Wu-Sheng Feng, and Shen-Iuan Liu, “A 2.4GHz low voltage CMOS down-conversion double-balanced mixer,” IEICE Trans. on Electronics, Vol. E84-C, pp. 1084-1091, Aug. 2001
  138. Cheng-Chieh Chang, Ming-Lang Lin and Shen-Iuan Liu, “CMOS current-mode exponential-control variable-gain amplifier,” Electronics Letters, vol. 37, pp. 868-869, Jun. 2001
  139. Shen-Iuan Liu, Tzong-Bang Yu and Hen-Wai Tsao, “Pipeline direct digital frequency synthesizer using decomposition method,” IEE Proceedings-Circuits Devices and Systems, vol. 148, pp. 141-144, Jun. 2001
  140. Chih-Chun Tang and Shen-Iuan Liu, “Low voltage CMOS low noise amplifier using the planar interleaved transformer,” Electronics Letters, vol. 37, pp. 497-498, Apr. 2001
  141. Jiin-Long Lee and Shen-Iuan Liu, “Integrator and differentiator with time constant multiplication Using a current feedback amplifier,” Electronics Letters, vol. 37, pp. 331-333, Mar. 2001
  142. Ching-Yuan Yang and Shen-Iuan Liu, “A one-wire approach for skew compensating clock distribution based on bidirectional techniques,” IEEE Journal of Solid-State Circuits, SC-36, pp. 266-272, Feb. 2001
  143. Cheng-Chieh Chang, Yuh-Shyang Hwang and Shen-Iuan Liu, “Low-voltage analog tripler circuit,” Journal of Analog Integrated Circuits and Signal Processing, vol. 26, pp. 125-128, Feb. 2001
  144. Ming-Huang Liu and Shen-Iuan Liu, “An 8-bit 10MS/s folding and interpolating ADC using the continuous-time auto-zero technique,” IEEE Journal of Solid-State Circuits, SC-36, pp. 122-128, Jan. 2001
  145. Cheng-Chieh Chang and Shen-Iuan Liu, “Pseudo-exponential function using MOSFETs in saturation,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 1318-1321, Nov. 2000
  146. Ching-Yuan Yang and Shen-Iuan Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE Journal of Solid-State Circuits, SC-35, pp. 1445-1452, Oct. 2000
  147. PoKi Chen, Shen-Iuan Liu and Jingshown Wu, “A CMOS pulse-shrinking delay element for time interval measurement,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp.954-958, Sept. 2000
  148. Cheng-Chieh Chang and Shen-Iuan Liu, “Current-mode full-wave rectifier and vector summation circuit,” Electronics Letters, vol. 36, pp. 1599-1600, Sept. 2000
  149. Cheng-Chieh Chang and Shen-Iuan Liu, “Current-mode pseudo-exponential circuit with tunable input range,” Electronics Letters, vol. 36, pp. 1335-1336, Aug. 2000
  150. Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, and Shen-Iuan Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE Journal of Solid-State Circuits, SC-35, pp. 1128-1136, Aug. 2000
  151. Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu and Shen-Iuan Liu, “A 900-MHz/1-V CMOS frequency synthesizer,” IEEE Journal of Solid-State Circuits, SC-35, pp. 1211-1214, Jul. 2000
  152. Guo-Ming Sung , Jian-Fan Wei and Shen-Iuan Liu, “Three types of 2-D lateral magneto-resistive sensors with P+-implant confinement,” IEE Proceedings-Circuits Devices and Systems, vol. 147, pp. 158-164, Jun. 2000
  153. Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tasi and Jingshown Wu, “A double sampling pseudo-2-path bandpass delta-sigma modulator,” IEEE Journal of Solid-State Circuits, pp. 276-280, Feb. 2000
  154. Weihsing Liu, Cheng-Chieh Chang, and Shen-Iuan Liu, “Realization of exponential V-I converter using composite NMOS transistors,” Electronics Letters, Vol. 36, pp. 8-10, Jan. 2000
  155. Jiin-Long Lee and Shen-Iuan Liu, “Dual-input RC integrator and differentiator with tunable time constants using current-feedback amplifiers,” Electronics Letters, Vol. 35, pp. 1910-1911, Oct. 1999
  156. Shen-Iuan Liu, Jiin-Long Lee and, Cheng-Chieh Chang, “Low-voltage BiCMOS four-quadrant multiplier and squarer,” Journal of Analog Integrated Circuits and Signal Processing, pp. 25-29, Jul. 1999
  157. Shen-Iuan Liu, Jiin-Long Lee and Cheng-Chieh Chang, “Low-voltage BiCMOS four-quadrant multiplier using triode-region transistors,” IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, vol. 46, pp. 861-864, Jul. 1999
  158. Shen-Iuan Liu, Jian-Fan Wei and Guo-Ming Sung,, “Spice Macro model for MAGFET and its applications,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, pp. 370-375, Apr. 1999
  159. Shen-Iuan Liu, Jiunn-Hwa Lee and Hen-Wai Tsao, “Low-power clock-deskew buffer for high-speed digital circuits,” IEEE Journal of Solid-State Circuits, SC-34, pp. 554-558, Apr. 1999
  160. Cheng-Chieh Chang and Shen-Iuan Liu, “Analogue BiCMOS squarer and its applications,” Electronics Letters, vol. 35, pp. 361-363, Mar. 1999
  161. Yu-Hsuan Chiang and Shen-Iuan Liu, “A submicrowatt 1.1MHz CMOS relaxation oscillator with temperature compensation,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 60, pp. 837-841
  162. Yu-Hsuan Chiang and Shen-Iuan Liu, “Nanopower CMOS relaxation oscillators with sub-100ppm/oC temperature coefficient,” IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, pp. 661-665

Conference & proceeding papers:

  1. Yu-Ming Ying, I-Ting Lee and Shen-Iuan Liu, “A 20Gb/s adaptive duobinary transceiver,” Asian Solid-State Circuits Conference (A-SSCC), pp. 129-132, Japan, Nov. 2012
  2. I-Ting Lee, Yun-Ta Tsai and Shen-Iuan Liu, “A fast-locking phase-locked loop using CP control and gated VCO,” International Symposium on VLSI Design, Automation & Test, pp. 1-4, Taiwan, Apr. 2012
  3. Liang-Hsin Chen, Min-Han Hsieh, Shen-Iuan Liu, and Charlie Chung-Ping Chen, “A 6.7 MHz-to-1.24 GHz 0.0318 mm^2 fast-locking all-digital DLL in 90 nm CMOS,” International Solid-State Circuits Conference (ISSCC), pp. 244-245, USA, Feb. 2012
  4. Yi-Chieh Huang and Shen-Iuan Liu, “A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing,” International Solid-State Circuits Conference (ISSCC), pp. 338-339, USA, Feb. 2012
  5. I-Ting Lee, Chiao-Hsing Wang, and Shen-Iuan Liu, “3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 93-96, Korea, Nov. 2011
  6. I-Ting Lee, Yun-Ta Tsai, and Shen-Iuan Liu, “A leakage-current-recycling phase-locked loop in 65nm CMOS technology,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 137-140, Korea, Nov. 2011
  7. Chang-Lin Hsieh and Shen-Iuan Liu, “A 40Gb/s adaptive receiver with linear equalizer and merged DFE/CDR,” Symposium on VLSI Circuits, pp. 208-209, Japan, Jun. 2011
  8. Yu-Ming Ying and Shen-Iuan Liu, “A 20Gb/s digitally adaptive equalizer/DFE with blind sampling,” International Solid-State Circuits Conference (ISSCC), pp. 444-445, USA, Feb. 2011
  9. Yi-Chieh Huang and Shen-Iuan Liu, “A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization,” Solid-State Circuits Conference (ISSCC), pp. 356-357, USA, Feb. 2011
  10. Bo-Yu Lin, I-Ting Lee, Chiao-Hsing Wang, and Shen-Iuan Liu, “A 198.9GHz ~201.0GHz injection-locked frequency divider in 65nm CMOS,” 2010 Symposium on VLSI Circuits, pp. 49-50, USA, Jun. 2010
  11. I-Hsin Wang, and Shen-Iuan Liu, “An integrating analog-to-digital data converter with variable resolution,” nternational Symposium on VLSI Design, Automation & Tes, pp. 186-189, Taiwan, Apr. 2010
  12. Chao-Ching Hung, I-Fong Chen and Shen-Iuan Liu, “A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression,” International Symposium on VLSI Design, Automation & Test, pp. 237-240, Taiwan, Apr. 2010
  13. Chao-Ching Hung, and Shen-Iuan Liu, “A 35.56GHz all-digital phase-locked loop with high resolution varactors,” International Symposium on VLSI Design, Automation & Test, pp. 245-248, Taiwan, Apr. 2010
  14. Hong-Lin Chu, Chang-Lin Hsieh and Shen-Iuan Liu, “A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13um CMOS,” IEEE Asian Solid-State Circuits Conference, pp. 165-168, Taiwan, Nov. 2009
  15. Wei-Ming Lin, Chan-Fei Lin, and Shen-Iuan Liu, “A CBSC second-order sigma-delta modulator in 3um LTPS-TFT Technology,” IEEE Asian Solid-State Circuits Conference, pp. 113-116, Taiwan, Nov. 2009
  16. Wei-Ming Lin, Kuang-Fu Teng, and Shen-Iuan Liu, “A delay-locked loop with digital background calibration,” IEEE Asian Solid-State Circuits Conference, pp. 317-320, Taiwan, Nov. 2009
  17. I-Fong Chen, Rong-Jyi Yang, and Shen-Iuan Liu, “Loop latency reduction technique for all-digital clock and data recovery circuits,” IEEE Asian Solid-State Circuits Conference, pp. 309-312, Taiwan, Nov. 2009
  18. Bo-Yu Lin, and Shen-Iuan Liu, “A 132.7-to-143.5GHz injection-locked frequency divider in 65nm CMOS,” Symposium on VLSI Circuits, pp. 230-231, Japan, Jun. 2009
  19. Chang-Lin Hsieh, and Shen-Iuan Liu, “A 40Gb/s decision feedback equalizer using back-gate feedback technique,” Symposium on VLSI Circuits, pp. 218-219, Japan, Jun. 2009
  20. Hwei-Yu Lee and Shen-Iuan Liu, “A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage,” IEEE International Symposium on Circuits and Systems, pp. 976-979, Taiwan, May 2009
  21. Wei-Jen Huang, Chein-Lung Chen, and Shen-Iuan Liu, “A wireless power telemetry with self-calibrated resonant frequency,” International Symposium on VLSI Design, Automation & Test, pp. 80-83, Taiwan, Apr. 2009
  22. Jung-Yu Chang, Che-Wei Fan, and Shen-Iuan Liu, “A frequency synthesizer for mode-1 MB-OFDM UWB applications,” International Symposium on VLSI Design, Automation & Test, pp. 219-222, Taiwan, Apr. 2009
  23. Wei-Ming Lin, Chao-Chyun Chen, and Shen-Iuan Liu, “An all-digital clock generator for dynamic frequency scaling,” International Symposium on VLSI Design, Automation & Test, pp. 251-254, Taiwan, Apr. 2009
  24. Chao-Ching Hung, and Shen-Iuan Li, “A leakage-suppression technique for phase-locked systems in 65nm CMOS technology,” International Solid-State Circuits Conference, pp. 400-401, USA, Feb. 2009
  25. Bo-Yu Lin, Kun-Hung Tsai, and Shen-Iuan Liu, “A 128.24~137.00GHz injection-locked frequency divider in 65nm CMOS,” International Solid-State Circuits Conference, pp. 282-283, USA, Feb. 2009
  26. Kun-Hung Tsai, and Shen-Iuan Liu, “A 43.7mW 96GHz phase-locked loop in 65nm CMOS technology,” International Solid-State Circuits Conference, pp. 276-277, USA, Feb. 2009
  27. Chao-Ching Hung, Chihun Lee, Lan-Chou Cho, and Shen-Iuan Liu, “A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 413-416, Japan, Nov. 2008
  28. Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu, “A 15-20GHz delay-locked loop in 90nm CMOS technology,” IEEE Asian Solid-State Circuits Conference (A-SSCC, pp. 213-216, Japan, Nov. 2008
  29. I-Hsin Wang and Shen-Iuan Liu, “A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 377-380, Japan, Nov. 2008
  30. Wei-Jen Huang and Shen-Iuan Liu, “A sub-1V low-dropout regulator with an on-chip voltage reference,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 165-168, Japan, Oct. 2008
  31. Hong-Lin Chu, Chaung-Lin Hsieh, and Shen-Iuan Liu, “20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 429-433, Japan, Oct. 2008
  32. Ding-Shiuan Shen, Chao-Ching Hung and Shen-Iuan Liu, “A 40GHz fractional-N frequency synthesizer in 0.13um CMOS,” The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 295-299, USA, Jun. 2008
  33. Kun-Hung Tsai, Jia-Hao Wu, and Shen-Iuan Liu, “A digitally calibrated 64.3-66.2GHz phase-locked loop,” The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 307-310, USA, Jun. 2008
  34. Kun-Hung Tsai, Jia-Hao Wu, and Shen-Iuan Liu, “ Frequency dividers with enhanced locking range,” The 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 661-663, USA, Jun. 2008
  35. Lan-Chou Cho, Kun-Hung Tsai, Chao-Ching Hung, and Shen-Iuan Liu, “93.5~ 109.4GHz CMOS injection-locked frequency divider with 15.3% locking range,” 2008 Symposium on VLSI Circuits, pp. 86-87, USA, Jun. 2008
  36. Jian-Hao Lu, Ke-Hou Chen, An-Ming Lee, Ting-Ying Wu, and Shen-Iuan Liu, “A merged CMOS digital near-end crosstalk canceller and analog equalizer for multi-lane serial-link receivers,” 2008 Symposium on VLSI Circuits, pp. 56-57, USA, Jun. 2008
  37. Ke-Hou Chen, Chihun Lee and Shen-Iuan Liu, “A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology,” 2008 Symposium on VLSI Circuits, pp. 160-161, USA, Jun. 2008
  38. Jian-Hao Lu, Ke-Hou Chen, and Shen-Iuan Liu, “A 40Gb/s low-power analog equalizer in 0.13μm CMOS technology,” 2008 Symposium on VLSI Circuits, pp. 54-55, USA, Jun. 2008
  39. . Kun-Hung Tsai and Shen-Iuan Liu, “A 62-66.1GHz phase-locked loop in 0.13um technology,” International Symposium on VLSI Design, Automation & Test, Taiwan, Apr. 2008
  40. Che-Fu Liang and Shen-Iuan Liu, “A 20/10/5/2.5Gbps power-scaling burst-mode CDR circuit using GVCO/Div2/DFF tri-mode cells,” International Solid-State Circuits Conference, pp. 224-225, Feb. 2008
  41. Chih-Fan Liao and Shen-Iuan Liu, “A 40-Gb/s CMOS serial-link receiver with adaptive equalization and CDR,” International Solid-State Circuits Conference, pp. 100-101, Feb. 2008
  42. Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu and Shen-Iuan Liu, “3.5mW W-band fequency divider with wide locking range in 90-nm CMOS technology,” International Solid-State Circuits Conference, pp. 466-467, Feb. 2008
  43. Shao-Hung Lin, Chang-Lin Hsieh and Shen-Iuan Liu, “A half-rate bang-bang phase/frequency detector for continuous-rate CDR circuits,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.353-356, Dec. 2007
  44. Kun-Hung Tsai and Shen-Iuan Liu, “A 39.2~45.5GHz frequency divider using a switched cross-coupled pair,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 409-412, Dec. 2007
  45. Shao-Ku Kao, and Shen-Iuan Liu, “A wide-range all-digital duty cycle corrector with a period monitor,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 349-352, Dec. 2007
  46. Shao-Ku Kao, and Shen-Iuan Liu, “A fast-locked all-digital delay-locked loop with non-50% input duty cycle,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp.1125-1128, Dec. 2007
  47. Hwei-Yu Lee, and Shen-Iuan Liu, “A 8-bit 140MS/s pipelined ADC using folded sample-and-hold stage,” International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 357-360, Dec. 2007
  48. Jian-Hao Lu, Chi-Lun Luo, and Shen-Iuan Liu, “A 10Gb/s analog equalizer in 0.18μm CMOS technology,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 404-407, Nov. 2007
  49. Chao-Chyun Chen and Shen-Iuan Liu, “An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 448-451, Nov. 2007
  50. Hong-Lin Chu and Shen-Iuan Liu, “A 10Gb/s burst-mode transimpedance amplifier in 0.13μm CMOS,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 400-403, Nov. 2007
  51. Wei-Ming Lin and Shen-Iuan Liu, “An all-digital reused-SAR delay-locked loop with adjustable duty cycle,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 312-315, Nov. 2007
  52. Ke-Hou Chen, Jian-Hao Lu and Shen-Iuan Liu, “A 2.4GHz efficiency-enhanced rectifier for wireless telemetry,” IEEE Custom Integrated Circuits Conference, Sept. 2007
  53. Hwei-Yu Lee and Shen-Iuan Liu, “A 10-bit 100MS/s pipelined ADC in 0.18µm CMOS technology,” IEEE International SOC Conference, pp. 3-6, Sept. 2007
  54. Hwei-Yu Lee, I-Hsin Wang, and Shen-Iuan Liu, “A 7-bit 400MS/s sub-ranging flash ADC in 0.18um CMOS,” IEEE International SOC Conference, pp. 11-14, Sept. 2007
  55. Che-Fu Liang, Sy-Chyuan Hwu and Shen-Iuan Liu, “A jitter-tolerance-enhanced CDR using a GDCO-based phase detector,” 2007 Symposium on VLSI Circuits, pp. 274-275, Jun. 2007
  56. I-Hsin Wang and Shen-Iuan Liu, “A 4-bit, 13.5GSample/sec track-and-hold circuit,” International Symposium on VLSI Design, Automation & Test, pp.144-147, Taiwan, Apr. 2007
  57. I-Hsin Wang and Shen-Iuan Liu, “A 1V 5-bit 5GSample/sec CMOS ADC for UWB receivers,” International Symposium on VLSI Design, Automation & Test, pp. 140-143, Taiwan, Apr. 2007
  58. Jung-Yu Chang and Shen-Iuan Liu, “A 4-54GHz static frequency divider with back-gate coupling,” International Symposium on VLSI Design, Automation & Test, pp. 212-215, Taiwan, Apr. 2007
  59. Chihun Lee and Shen-Iuan Liu, “A 58-to-60.4GHz frequency synthesizer in 90nm CMOS,” International Solid-State Circuits Conference (ISSCC) 2007, pp. 196-197, USA, Feb. 2007
  60. Chi-Nan Chuang and Shen-Iuan Liu, “A 40GHz DLL-based clock generator in 90nm CMOS technology,” International Solid-State Circuits Conference (ISSCC) 2007, pp. 178-179, USA, Feb. 2007
  61. Lan-Chou Cho, Chihun Lee and Shen-Iuan Liu, “A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS,” International Solid-State Circuits Conference (ISSCC) 2007, pp.48-49, USA, Feb. 2007
  62. Chih-Fan Liao and Shen-Iuan Liu, “A 40Gb/s Transimpedance-AGC amplifier with 19dB DR in 90nm CMOS,” International Solid-State Circuits Conference (ISSCC) 2007, pp.54-55, USA, Feb. 2007
  63. Rong-Jyi Yang, and Shen-Iuan Liu, “A 2.5GHz, 30mW, 0.03mm2, all-digital delay-locked loop,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 271-274, China, Oct. 2006
  64. Chihun Lee, Lan-Chou Cho and Shen-Iuan Liu, “A 44GHz dual-modulus divide-by-4/5 prescaler in 90nm CMOS technology,” IEEE Custom Integrated Circuits Conference, pp. 397-400, USA, Sept. 2006
  65. Che-Fu Liang, Sy-Chyuan Hwu and Shen-Iuan Liu, “A 10Gbps burst-mode CDR circuit in 0.18μm CMOS,” IEEE Custom Integrated Circuits Conference, pp. 599-602, USA, Sept. 2006
  66. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, “A capacitor multiplication technique using a second-generation current conveyor,” 17th VLSI Design/CAD Symposium, Taiwan, Session B3, Taiwan, Aug. 2006
  67. Chihun Lee and Shen-Iuan Liu, “A 35-Gb/s limiting amplifier in 0.13um CMOS technology,” 2006 Symposium on VLSI Circuits, USA, pp. 152-153, Jun. 2006
  68. Chihun Lee, Lan-Cho Chou and Shen-Iuan Liu, Chun-Lin Ko, Ying-Zong Juang, Chin-Fong Chiu, “A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology,” 2006 Symposium on VLSI Circuits, pp. 34-35, USA, Jun. 2006
  69. Yen-Horng Chen, Chih-Wei Wang, Ching-Feng Lee, Jen-Lung Liu, Tzu-Yi Yang, Chih-Fan Liao, Che-Fu Liang, Gin-Kou Ma, Shen-Iuan Liu, “A 0.18μm CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems,” 2006 RFIC Symposium, RMO4B-1, pp. 297-300, Jun. 2006
  70. Jian-Hao Lu, Ke-Hou Chen, and Shen-Iuan Liu, “A 40Gb/s low-power analog equalizer in 0.13μm CMOS technology,” 2008 Symposium on VLSI Circuits, Jun. 2006
  71. Chao-Chyun Chen, Sheng-Chou Lee and Shen-Iuan Liu, “A fully integrated spread spectrum clock generator,” International Symposium on VLSI Design, Automation & Test, pp. 191-194, Taiwan, Apr. 2006
  72. Wei-Jen Huang, Sao-Hung Lu, and Shen-Iuan Liu, “A capacitor-free CMOS low dropout regulator with slew rate enhancement,” International Symposium on VLSI Design, Automation & Test, pp. 211-214, Taiwan, Apr. 2006
  73. Bo-Jiun Chen, Shao-Ku Kao, and Shen-Iuan Liu, “An all-digital duty cycle corrector,” International Symposium on VLSI Design, Automation & Test, pp. 195-198, Taiwan, Apr. 2006
  74. Jian-Hao Lu, Chi-Lun Luo, and Shen-Iuan Liu, “An adaptive 3.125Gbps coaxial cable equalizer,” International Symposium on VLSI Design, Automation & Test, pp. 219-222, Taiwan, Apr. 2006
  75. Chih-Fan Liao and Shen-Iuan Liu, “A 10Gb/s CMOS automatic gain control amplifier with 35dB dynamic range for 10Gigabit Ethernet,” International Solid-State Circuits Conference (ISSCC) 2006, pp. 516-517, USA, Feb. 2006
  76. Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang and Gin-Kou Ma, “A 14-band frequency synthesizer for MB-OFDM UWB application,” International Solid-State Circuits Conference (ISSCC) 2006, pp. 126-127, USA, Feb. 2006
  77. Sao-Hung Lu, Wei-Jen Huang, and Shen-Iuan Liu, “A fast settling low dropout linear regulator with single Miller compensation capacitor,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 153-156, Taiwan, Nov. 2005
  78. Tysh-Bin Liu, Wei-Jen Huang, and Shen-Iuan Liu, “A dual-phase digital PWM controller for DC-DC switching converters with current balancing,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 161-164, Taiwan, Nov. 2005
  79. Chihun Lee, Lan-Chou Cho, and Shen-Iuan Liu, “A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18-μm CMOS Technology,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 129-132, Taiwan, Nov. 2005
  80. Che-Fu Liang, Sy-Chyuan Hwu, and Shen-Iuan Liu, “A 2.5Gbps burst-mode clock and data recovery circuit,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 457-460, Taiwan, Nov. 2005
  81. Che-Fu Liang and Shen-Iuan Liu, “A fast-switching frequency synthesizer for UWB applications,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 197-200, Taiwan, Nov. 2005
  82. Che-Fu Liang, Shih-Tsai Liu, Hsiang-Hui Chang, and Shen-Iuan Liu, “A calibrated pulse generator for impulse-radio UWB applications,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 293-296, Taiwan, Nov. 2005
  83. Jung-Yu Chang, Chia-Hsin Wu, and Shen-Iuan Liu, “A low-phase-noise low-phase-error 2.4GHz CMOS quadrature VCO,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 281-284, Taiwan, Nov. 2005
  84. I-Hsin Wang, Wei-Sheng Chen, and Shen-Iuan Liu, “A 5Gbps CMOS automatic gain control amplifier for 10GBase-LX,” Proceedings of Technical Papers on IEEE Asian Solid-State Circuits, pp. 169-172, Taiwan, Nov. 2005
  85. Chih-Fan Liao and Shen-Iuan Liu, “A broadband noise-canceling CMOS LNA for 3.1–10.6-GHz UWB receiver,” IEEE Custom Integrated Circuits Conference, pp. 161 - 164, USA, Sept. 2005
  86. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, “Cycle slipping reduction technique in phase-locked loops,” 2005 VLSI/CAD Symposium, Session B3, Taiwan, Aug. 2005
  87. Hung-Chun Chen, Jung-Yu Chang, and Shen-Iuan Liu, “A 3.125-Gb/s laser driver for 10GBase-LX4 Ethernet,” 2005 VLSI/CAD Symposium, Poster Session P2, Taiwan, Aug. 2005
  88. Chao-Chyun Chen, Sheng-Chou Lee, and Shen-Iuan Liu, “A spread-spectrum clock generator using a capacitor multiplication technique,” The 5th Emerging Information Technology Conference (EITC 2005), Taiwan, Aug. 2005
  89. Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang and Hen-Wai Tsao, “A 15mW 69dB 2Gsamples/s CMOS analog front-end for low-band UWB applications,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 368-371, May 2005
  90. Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Shen-Iuan Liu, “A tunable bandpass DS modulator using double sampling,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3676-3679, May 2005
  91. Chihun Lee, Chia-Hsin Wu, and Shen-Iuan Liu, “A 1.2V 18mW 10Gb/s SiGe transimpedance amplifier,” AP-ASIC 2004, Session 14-5, pp, Japan, Aug. 2004
  92. Rong-Jyi Yang and Shen-Iuan Liu, “A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector,” AP-ASIC 2004, Session 14-5, p, Japan, Aug. 2004
  93. I-Hsin Wang, Chung-Shun Liu, and Shen-Iuan Liu, “A low power 5Gb/s transimpedance amplifier with dual feedback technique,” AP-ASIC 2004, Session 14-6, pp, Japan, Aug. 2004
  94. Chun-Yi Kuo, Che-Fu Liang, and Shen-Iuan Liu, “ 5.8-/5.2-/2.4-GHz SiGe LC VCO with Wide Tuning Range,” 2004 VLSI/CAD Symposium, B2-2, Taiwan, Aug. 2004
  95. Jung-Yu Chang, and Shen-Iuan Liu, “An AC-coupled Quadrature LC tank VCO,” 2004 VLSI/CAD Symposium, B2-1, Taiwan, Aug. 2004
  96. Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, and Hen-Wai Tsao, “CMOS Low-Band UWB Analog Front-End,” 2004 VLSI/CAD Symposium, P-49, Taiwan, Aug. 2004
  97. Chia-Hsin Wu, Jieh-Wei Liao, and Shen-Iuan Liu, “A 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors,” International Symposium on Circuits and Systems (ISCAS), Vol. I, pp. 1044, Canada, May 2004
  98. Chia-Hsin Wu, Chang-Shun Liu, and Shen-Iuan Liu, “A 2GHz CMOS Variable-Gain Amplifier with 50dB Linear-in-Magnitude Controlled Gain Range for 10GBase-LX4 Ethernet,” International Solid-State Circuits Conference (ISSCC) 2004, pp. 484-485, USA, Feb. 2004
  99. Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu, “A Shifted-Averaging VCO with Precise Multiphase Outputs and Low Jitter Operation,” 29th European Solid-State Circuits Conference, CP17, Sept. 2003
  100. Chia-Hsin Wu, Jieh-Wei Liao, Chih-Hun Lee, and Shen-Iuan Liu, “ 1V 4.2mW Fully Integrated 2.5Gb/s CMOS Limiting Amplifier using Folded Active Inductors,” 2003 VLSI/CAD, pp. 49-52, Taiwan, Aug. 2003
  101. Chien-Hung Kuo, Tsung-Kai Kao, and Shen-Iuan Liu, “A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator,” 2003 VLSI/CAD, pp. 201-204, Taiwan, Aug. 2003
  102. Hsiang-Hui Chang, Chih-Hao Sun, and Shen-Iuan Liu, “Low Jitter Butterworth Delay-Locked Loops,” 2003 Symposium on VLSI Circuits, pp.177-180, Jun. 2003
  103. Chia-Hsin Wu, Chun-Yi Kuo, and Shen-Iuan Liu, “Selective Metal Parallel Shunting Inductor and Its VCO Application,” 2003 Symposium on VLSI Circuits, pp.37-40, Jun. 2003
  104. Hsiang-Hui Chang, Chih-Hao Sun, and Shen-Iuan Liu, “A Low Jitter and Precise Multiphase Delay-Locked Loop Using Shifted Averaging VCDL,” ISSCC 2003, pp. 434-435, Feb. 2003
  105. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, “Image rejection relaxed 5GHz CMOS receiver front-end,” 2002 VLSI/CAD, pp. 47-50, Taiwan, Aug. 2002
  106. Rong-Jyi Yang, Ming-Zhe Liu and Shen-Iuan Liu, “Gigahertz CMOS monolithic frequency synthesizer,” 2002 VLSI/CAD, pp. 232-235, Taiwan, Aug. 2002
  107. Lan-Cho Chou, Chih-Hao Sun, and Shen-Iuan Liu, “Low-jitter DLLs with the butterworth characteristics,” 2002 VLSI/CAD, pp. 252-255, Taiwan,, Aug. 2002
  108. Hsiang-Hui Chang, Shang-Ping Chen, Kuang-Wei Cheng and Shen-Iuan Liu, “A 0.8V switched-opamp bandpass delta sigma modulator using a two-path architecture,” 2002 IEEE ASIA-PACIFIC Conference on ASIC, pp. 1-4, Aug. 2002
  109. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, “Analysis of on-chip spiral inductors using distributed capacitance model,” 2002 IEEE ASIA-PACIFIC Conference on ASIC, pp. 259-262, Aug. 2002
  110. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A wide-range and fixed latency of one clock cycle delay-lock looped loop,” IEEE ISCAS 2002, vol. III, pp. 67, May 2002
  111. Chia-Hsin Wu,Chih-Chun Tang, and Shen-Iuan Liu, “Analysis and application of miniature 3D inductor,” IEEE ISCAS 2002, vol. II, pp. 811, May 2002
  112. Chih-Chun Tang, and Shen-Iuan Liu, “CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90-degree delay network,” IEEE ISCAS 2002, vol. III, pp. 77, May 2002
  113. Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang and Shen-Iuan Liu, “A Wide-range and Fixed Latency of One Clock Cycle Delay-Lock Looped Loop,” IEEE CICC 2002, pp. 49-52, May 2002
  114. Chih-Chun Tang and Shen-Iuan Liu, “A 1V 5.8GHz CMOS Low Noise Amplifier in a 0.35um CMOS Process,” accepted by 2001 International Symposium on Communications, Tainan, Taiwan, Nov. 2001
  115. Chih-Chun Tang, Chia-Hsin Wu, Chi-Kun Chiu, Shen-Iuan Liu, “Analysis and Application of Miniature 3D Inductor,” 12 th VLSI Design/CAD Symposium, B3-1, Taiwan, R.O.C., Session: RF ICs, Sensors and Actuators, Aug. 2001
  116. Shr-Lung Chen, Hsiang-Hui Chang, Kun-Hsien Li, Shen-Iuan Liu, “CMOS Magnetic to Digital Converter Using  Oversampling ModulatorCMOS Magnetic to Digital Converter Using  Oversampling Modulator,” 12 th VLSI Design/CAD Symposium, B3-4, Taiwan, R.O.C., Session: RF ICs, Sensors and Actuators, Aug. 2001
  117. Chia-Hsin Wu, Chih-Chun Tang, Shen-Iuan Liu, “A 2.4GHz CMOS LNA with New Area-Efficient Inductor,” 12 th VLSI Design/CAD Symposium, B3-10, Taiwan, R.O. C., Session: RF ICs, Sensors and Actuators, Aug. 2001
  118. Giang-Kaai Dehng,Jyh-Woei Lin and Shen-Iuan Liu, “A Fast-lock Mixed-mode DLL Using a 2-b SAR Algorithm,” IEEE Custom Integrated Circuits Conference, pp. 489-492, May 2001
  119. Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng and Shen-Iuan Liu, “A 2.4-GHz CMOS Down-Conversion Doubly Balanced Mixer with Low Supply Voltage,” the International Symposium on Circuits and Systems (ISCAS), Vol. IV, pp. 74, Sydney, May 2001
  120. Lee-An Ho , Shr-Lung Chen , Chien-Hung Kuo, and Shen-Iuan Liu, “CMOS Oversampling Delta-Sigma Magnetic to Digital Converters,” IEEE International Symposium on Circuits and Systems (ISCAS), Vol. I, pp. 388-, Sydney, May 2001
  121. Jian-Ming Yang, Chi-Kun Chiu, and Shen-Iuan Liu, “A 2.4GHz CMOS LC-Tank Voltage-Controlled Oscillator,” the 11th VLSI/CAD symposium, pp. 269-272, Taiwan, R.O.C, Aug. 2000
  122. Yu-Shun Huang, Chia-Shin Wu, and Shen-Iuan Liu, “2.4-GHz CMOS RF Front-End Receiving Circuits,” the 11th VLSI/CAD symposium, pp. 261-264, Taiwan, R.O.C, Aug. 2000
  123. Chorng-Sii Hwang, Wang-Chih Chung, Chih-Yung Wang, C. Wang, Hen-Wai Tsao and Shen-Iuan Liu, “A 2V Clock Synchronizer using Digital Delay-Locked Loop,” AP-ASIC, Korea, Aug. 2000
  124. Guang-Kaai Dehng, Wei-Hung Chen, Jong-Woei Chen and Shen-Iuan Liu, “A CMOS 455 Mbps/channel LVDS Receiver for Flat Panel Display,” the 10th VLSI/CAD symposium, pp. 365-368, Taiwan, R.O.C, Aug. 1999
  125. Guang-Kaai Dehng, Jong-Woei Chen, Wei-Hung Chen and Shen-Iuan Liu, “High Speed CMOS Interface Circuits for IEEE-1394 High Performance Serial Bus,” the 10th VLSI/CAD symposium, pp. 221-222, Taiwan, R.O.C, Aug. 1999
  126. PoKi Chen and Shen-Iuan Liu, “A cyclic CMOS time-to-digital converter with deep subnanosecond resolution,” Proceedings of IEEE Custom Integarted Circuits Conference, pp. 605-608, May 1999
  127. Guang-Kaai Dehng and Shen-Iuan Liu, “A 750MHz/1V 128/129 prescaler using a voltage doubler,” 1999 International analog VLSI workshop, pp. 57-61, May 1999
  128. June-Ming Hsu, Shen-Iuan Liu, Ching-Yuan Yang and Guang-Kaai Dehng, “A 1V CMOS dynamice back-gate forward bias prescaler for frequency synthesizer application,” 1999 International analog VLSI workshop, pp. 45-50, May 1999

Books:

  1. 劉深淵與楊清淵, “鎖相迴路,” 滄海書局, 中華民國, 477 pages, Nov. 2006

Patents:

  1. 陳伯奇,劉深淵,吳靜雄, “具深次奈秒解析度之互補式金氧半脈衝縮減延遲元件,” 中華民國 130413, Apr. 2001
  2. 劉深淵, “低電壓具抵補電壓補償之切換電容積分器及濾波器,” 美國 6169440B1, Mar. 2001
  3. 劉深淵, “低電壓具抵補電壓補償之切換電容積分器及濾波器,” 中華民國 129907, Mar. 2001
  4. 劉深淵,吳靜雄,黃育賢, “利用偏壓回饋技術之金氧半四象限乘法,” 美國 6208192B1, Mar. 2001
  5. 楊清淵,劉深淵,陳良基, “High-frequency CMOS dual/multimodulus prescaler,” 美國 6094466, Jan. 2001
  6. 蔡瑞原,劉深淵, 吳靜雄, “雙倍取樣暨虛擬三通路帶通積分三角調變器,” 美國 6172631B1, Jan. 2001
  7. 陳伯奇,劉深淵,曹恆偉,吳靜雄, “信號處理裝置,” 美國 6118390, Sept. 2000
  8. 楊清淵,劉深淵.陳良基, “高頻互補式金氧半雙模/多模前置分頻器,” 中華民國 114359, Aug. 2000
  9. 蔡瑞原,劉深淵,吳靜雄, “雙倍取樣暨虛擬三通路帶通積分三角調變器,” 中華民國 115348, May 2000
  10. 劉深淵, “低電壓互補式金氧半三輸入乘法器,” 中華民國 107570, Apr. 2000
  11. 游宗榜,劉深淵,曹恆偉, “Direct Digital Frequency Synthesizer,” 美國 5986483, Nov. 1999
  12. 楊清淵,劉深淵, “除4/5電路,” 中華民國 107136, Aug. 1999
  13. 陳伯奇,劉深淵,曹恆偉,吳靜雄, “信號處理裝置,” 中華民國 100449, Jul. 1999
  14. 楊清淵劉深淵, “Divide by 4/5 counter,” 美國 5930322, Jul. 1999
  15. 劉深淵,黃育賢, “類比排序與中值電路,” 中華民國 102377, Apr. 1999
  16. 游宗榜,劉深淵,曹恆偉, “直接數位頻率合成器,” 中華民國 96435, Nov. 1998
  17. 劉深淵, “CMOS Low-voltage Four-Quadrant Multiplier,” 美國 5,656,964, Aug. 1998
  18. 劉深淵, “Four-Quadrant Three-Input Multiplier,” 美國 5,602,504, Aug. 1997
  19. 劉深淵,吳靜雄,黃育賢, “利用金氧半電晶體於飽和區之平方律特性之金氧半四象限乘法器與平方器,” 中華民國 80932, Sept. 1996
  20. 劉深淵, “互補式金氧半雙差動電流運輸器及其應用之積分電路和濾波電路,” 中華民國 79,061, Jun. 1996
  21. 劉深淵, “Vector Summation Device,” 美國 5,506,538, Apr. 1996
  22. 劉深淵, “向量和裝置,” 中華民國 76,707, Feb. 1996
  23. 劉深淵,吳靜雄, “利用偏壓回受技術之金氧半四象限乘法,” 中華民國 79,959, Jan. 1996
  24. 劉深淵, “Differential-difference current conveyor applications,” 美國 5,596,289, Jan. 1996
  25. 劉深淵, “四象限乘法器,” 中華民國 74,211, Oct. 1995
  26. 劉深淵, “Four-Quadrant Multiplier,” 美國 5,557,228, Oct. 1995
  27. 劉深淵, “互補式金氧半低電壓四象限乘法器,” 中華民國 72,138, Jul. 1995
  28. 劉深淵,吳靜雄,曹恆偉, “交換電流微分器及其濾波器應用,” 中華民國 59,072, Oct. 1992
  29. 劉深淵,吳靜雄,曹恆偉, “CMOS current conveyor and its filter applications,” 美國 5,124,666, Jun. 1992
  30. 劉深淵,吳靜雄,曹恆偉, “互補式金氧半電流運輸器及其濾波器應用,” 中華民國 55,527, Apr. 1992
  31. 劉深淵,吳靜雄,曹恆偉, “Switched-current differentiator and its filter applications,” 美國 5,097,155, Mar. 1992
  32. 劉深淵,許峻銘, “低電壓動態背閘順偏前置分頻器,” 中華民國 136404, Apr. 1991

other:

  1. 劉深淵, “一個具有功率因素校正功能與減少輸入電流全諧波失真的交流直流轉換器,” Nov. 2005, 技術移轉至通嘉科技NT$50,000
  2. 劉深淵, “Fast-switching CMOS Frequency synthesizer,” Dec. 2001, 技術移轉至億兆公司NT$500,000
  3. 劉深淵, “RF devies and modeling,” Sept. 2001, 技術移轉至億兆公司NT$400,000
  4. 劉深淵, “Low voltage Pipelined Analog-to-Digital Converter,” 技術移轉至億兆公司NT$50,000