黃俊郎教授的著作列表 - Publication List of Jiun-Lang Huang

Publication List of 黃俊郎 Jiun-Lang Huang

Journal articles & book chapters:

  1. K.-W. Yeh, J.-L. Huang, L.-T. Wang, “CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator,” Journal of Electronic Testing: Theory and Applications, vo. 32, issue 5, 625-638~638, Oct. 2016
  2. Y.-Y. Chen, J.-L. Huang, T. Kuo, X.-L. Huang, “Design and Implementation of an FPGA-Based Data/Timing Formatter,” Journal of Electronic Testing: Theory and Applications, vo. 31, issue 5, 549-559~559, Dec. 2015
  3. T.-C. Huang, J.-L. Huang, and K.-T. Cheng, “Design, automation, and test for low-power and reliable flexible electronics,” Foundations and Trends in Electronic Design Automation, vol. 9, no. 2, 99~210, Jan. 2015
  4. T.-C. Huang, J.-L. Huang, K.-T. Cheng, “Design, Automation, and Test for Low-Power and Reliable Flexible Electronics,” Foundations and Trends in Electronic Design Automation, vol. 9, no. 2, 99-210~210, 2015
  5. H.-M. Chang, J.-L. Huang, K.-T. Cheng, “Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vo. 21, no. 3, 465-474~474, Mar. 2013
  6. H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Cheng, and C.-W. Wu, “A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers,” IEEE Transactions on Very Large Scale Integration, vo. 21, no. 3, 465-474, Mar. 2013
  7. S.-K. Lu, H.-H. Huang, J.-L. Huang, and P. Ning, “Synergistic reliability and yield enhancement techniques for embedded SRAMs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, 165~169, Jan. 2013
  8. S.-K. Lu, H.-H. Huang, J.-L. Huang, P. Ning, “Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, 165-169~169, Jan. 2013
  9. S. Wu, L.-T. Wang, X. Wen, W.-B. Jone, M.-S. Hsiao, F. Li, James C.-M. Li, and J.-L. Huang, “Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,” ACM Transactions on Design Automation of Electronic Systems, vol. 17, no. 4, 48:1-48:16, Oct. 2012
  10. X.-L. Huang, J.-L. Huang, H.-I. Chen, C.-Y. Chen, K.-T. Tseng, M.-F. Huang, Y.-F. Chou, and D.-M. Kwai, “An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration,” Journal of Electronic Testing: Theory and Applications, vol. 28, issue 5, pp. 705-722, Oct. 2012
  11. T.-C Huang, J.-L. Huang, and K.-T. Cheng, “Robust Circuit Design for Flexible Electronics,” IEEE Design & Test of Computers, vol. 28, no. 6, 8-15, Nov. 2011
  12. X.-L. Huang and J.-L. Huang, “ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling,” IEEE Transactions on Very Large Scale Integration, vol. 19, issue 10, 1765-1774, Oct. 2011
  13. M.-F. Wu, K.-S. Hu, and J.-L. Huang, “LPTest: A Flexible Low-Power Test Pattern Generator,” Journal of Electronic Testing: Theory and Applications, vol. 25, no. 6, 323-335, Dec. 2009
  14. M.-F. Wu, J.-L. Huang, X. Wen, and K. Miyase, “Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment,” IEEE Transactions on Compuuter-Aided Design, vol. 28, no. 11, 1767-1776, Nov. 2009
  15. X.-L. Huang, C.-Y. Yang, and J.-L. Huang, “A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input,” International Journal of Electrical Engineering, vol. 16, no. 5, 411-420, Oct. 2009
  16. C.-W. Lin and J.-L. Huang, “A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays,” Journal of Computers, vol. 4, no. 4, 338-346, Apr. 2009
  17. J.-L. Huang, C.-K. Koh, and S. F. Cauley, “Ch. 8 Logic and Circuit Simulation,” Electronic Design Automation: Synthesis, Verification, and Test, 2009
  18. J.-L. Huang, K.-T. Cheng, “Chap. 11 Software-Based Self-Testing,” System on Chip Test Architectures, 2007
  19. J.-L. Huang, “On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines,” Journal of Electronic Testing: Theory and Applications, Vol. 22, No. 4-6, 387-398, Dec. 2006
  20. J.-L. Huang, J.-J. Huang, and Y.-S. Liu, “A low-cost jitter measurement technique for BIST applications,” Journal of Electronic Testing: Theory and Appications, vol. 22, no. 3, 219-228, Jun. 2006
  21. J.-L. Huang, James C.-M. Li, and Duncan M. (Hank) Walker, “Chap. 3: Logic and Fault Simulation,” VLSI Test Principles and Architectures, Jun. 2006
  22. Y. R. Chen and J. L. Huang, “A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques,” Bulletin of the College of Engineering, National Taiwan University, 93, 63--70, Feb. 2005
  23. H. C. Hong, J. L. Huang, K. T. Cheng, C. W. Wu, and D. M. Kwai, “Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems,” IEEE Transactions on Circuits and Systems II, vol. 50, no. 9, pp. 553-566, Sept. 2003
  24. C. K. Ong, J. L. Huang, and K. T. Cheng, “Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns,” Microelectronics Journal, vol. 33, no. 10, pp. 807-814, Oct. 2002
  25. J. L. Huang, and K. T. Cheng, “Test point selection for analog fault diagnosis on unpowered circuit boards,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 2, pp. 977-987, Oct. 2000

Conference & proceeding papers:

  1. Y.-K. Huang, K.-T. Li, C.-L. Hsiao, C.-A. Lee, J.-L. Huang, T. Kuo, “Design and implementation of an EG-pool based FPGA formatter with temperature compensation,” Asian Test Symposium, Taipei, Taiwan, Nov. 2017
  2. T.-Y. Tsai, J.-L. Huang, “Source code transformation for software-based on-line error detection,” IEEE Conference on Dependable and Secure Computing, 305-309, Taipei, Taiwan, Aug. 2017
  3. P.-F. Hou, Y.-T. Lin, J.-L. Huang, A. Shih, Z. F. Conroy, “An IR-drop aware test pattern generator for scan-based at-speed testing,” Asian Test Symposium, 167-172, Hiroshima, Japan, Nov. 2016
  4. L.-Y. Hsu, J.-L. Huang, “A multi-channel FPGA-based time-to-digital converter,” International Mixed-Signal Testing Workshop, Catalunya, Spain, Jul. 2016
  5. L.-C. Tsai, J.-Z. Li, Y.-T. Lin, J.-L. Huang, A. Shih, Z. F. Conroy, “An IR-drop guided test pattern generation technique,” International Symposium on VLSI Design, Automation and Test, Hsinchu, Taiwan, Apr. 2016
  6. J.-H. Pan, K.-W. Yeh, J.-L. Huang, “A static bidirectional learning technique to accelerate test pattern generation,” International SoC Design Conference, Gyeongju, South Korea, Dec. 2015
  7. C.-H. Chang, K.-W. Yeh, J.-L. Huang, L.-T. Wang, “SDC-TPG: A deterministic zero-inflation parallel test pattern generator,” Asian Test Symposium, 43-48, Bombay, India, Nov. 2015
  8. G.-Y. Lin, and K.-H. Tsai, J.-L. Huang, and W.-T. Cheng, “A Test-Application-Count Based Learning Technique for Test Time Reduction,” International Symposium on VLSI Design, Automation, and Test, Hsinchu, Taiwan, 2015
  9. C.-Y. Wang, Y.-Y. Chen, J.-L. Huang, and X.-L. Huang, “FPGA-Based Subset Sum Delay Lines,” Asian Test Symposium, 287~291, Hangzhou, China, Nov. 2014
  10. S.-S. Lin, C.-L. Kao, J.-L. Huang, C.-C. Lee, and X.-L. Huang, “An IDDQ-Based Source Driver IC Design-for-Test Technique,” International Conference on Computer-Aided Design, 393~398, Nov. 2013
  11. S.-K. Lu, H.-C. Jheng, M. Hashizume, J.-L. Huang, and P. Ning, “Fault Scrambling Techniques for Yield Enhancement of Embedded Memories,” Asian Test Symposium, 215~220, Yilan, Taiwan, Nov. 2013
  12. K.-W. Yeh, J.-L. Huang, H.-J. Chao, and L.-T. Wang, “A circular pipeline processing based deterministic parallel test pattern generator,” International Test Conference, Anaheim, California, Sept. 2013
  13. Y.-Y. Chen, J.-L. Huang, and T. Kuo, “Implementation of programmable delay lines on off-the-shelf FPGAs,” IEEE AUTOTESTCON, 1~4, Sept. 2013
  14. H.-J. Lin, X.-L. Huang, and J.-L. Huang, “A mutual characterization based SAR ADC self-testing technique,” European Test Symposium, Avignon, France, May 2013
  15. J.-L. Huang, K.-H. Tsai, Y.-P. Liu, R. Guo, M. Sharma, and W.-T. Cheng, “Improve speed path identification with suspect path expressions,” International Symposium on VLSI Design, Automation, and Test, Hsinchu, Taiwan, Apr. 2013
  16. K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang, “On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression,” International Conference on VLSI Design, 279~284, Jan. 2013
  17. Y.-T. Lin, J.-L. Huang, and X. Wen, “A transition isolation scan cell design for low shift and capture power,” Asian Test Symposium, pp. 107-112, Niigata, Japan, Nov. 2012
  18. Y.-H. Chou, J.-L. Huang, and X.-L. Huang, “Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications,” Asian Test Symposium, 284-289, Niigata, Japan, Nov. 2012
  19. X.-L. Huang, J.-L. Huang, Y.-F. Chou, and D.-M. Kwai, “A SAR ADC missing-decision level detection and removal technique,” VLSI Test Symposium, pp. 31-36, Hawaii, USA, Apr. 2012
  20. B.-Y. Jan and J.-L. Huang, “A fault-tolerant PE array based matrix multiplier design,” International Symposium on VLSI Design, Automation, and Test, pp. 1-4, Hsinchu, Taiwan, Apr. 2012
  21. Y.-T. Lin, J.-L. Huang, and X. Wen, “Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing,” International Test Conference, paper 2.3, Anaheim, CA, USA, Sept. 2011
  22. W.-A. Lin, C.-C. Li, and J.-L. Huang, “Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs,” VLSI Test Symposium, Dana Point, California, May 2011
  23. X.-L. Huang, P.-Y. Kang, J.-L. Huang, Y.-F. Chou, Y.-P. Lee, and D.-M. Kwai, “A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager,” European Test Symposium, pp. 23-27, Trondheim, Norway, May 2011
  24. C.-J. Lin and J.-L. Huang, “Broadcast test pattern generation considering skew-insertion and partial-serial scan,” International Symposium on VLSI Design, Automation, and Test, HsinChu, Taiwan, Apr. 2011
  25. X.-L. Huang, P.-Y. Kang, H.-M. Chang, J.-L. Huang, Y.-F. Chou, Y.-P. Lee, D.-M. Kwai, and C.-W. Wu, “A self-testing and calibration method for embedded successive approximation register ADC,” Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 2011
  26. C.-Y. Liang, M.-F. Wu, and J.-L. Huang, “Power supply noise reduction in broadcast-based compression environment for at-speed scan testing,” Asian Test Symposium, 361-366, ShangHai, China, Dec. 2010
  27. M.-F. Wu, K.-H. Tsai, W.-T. Cheng, H.-C. Pan, J.-L. Huang, and A. Kifli, “A scalable quantitative measure of IR-drop for scan pattern generation,” International Conference on Computer-Aided Design, 162-167, San Jose, California, Nov. 2010
  28. H.-M. Sherman Chang, J.-L. Huang, D.-M. Kwai, K.-T. Cheng, and C.-W. Wu, “An Error Tolerance Scheme for 3D CMOS Imagers,” Design Automation Conference, 917-922, Anaheim, California, Jun. 2010
  29. [38] H.-M. Sherman Chang, J.-L. Huang, D.-M. Kwai, K.-T. Tim Cheng, and C.-W. Wu, “An Error Tolerance Scheme for 3D CMOS Imagers,” Design Automation Conference, Anaheim, CA, U.S.A., Jun. 2010
  30. Xuan-Lun Huang and Jiun-Lang Huang, “An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling,” VLSI Test Symposium, 289-294, Santa Cruz, USA, Apr. 2010
  31. L.-T. Wang, N. A. Touba, Z. Jiang, S. Wu, J.-L. Huang, and J.-M. Li, “CSER: BISER-Based Concurrent Soft-Error Resilience,” VLSI Test Symposium, 153-158, Santa Cruz, Apr. 2010
  32. J.-L. Huang, Kuo-Yu Chou, Ming-Huan Lu, and Xuan-Lun Huang, “A Robust ADC Code Hit Counter,” Design, Automation & Test in Europe, 1749-1754, Dresden, Germany, Mar. 2010
  33. H.-M. Sherman Chang, J.-L. Huang, D.-M. Kwai, K.-T. Tim Cheng, and C.-W. Wu, “3D-PIC: An Error Tolerant 3D CMOS Imager,” 3D Integration Workshop, Dresden, Germany, Mar. 2010
  34. M.-F. Wu, H.-C. Pan, T.-H. Wang, J.-L. Huang, K.-H., Tsai, and W.-T. Cheng, “An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation,” Asia and South Pacific Design Automation Conference, Taipei, Taiwan, Jan. 2010
  35. C.-Y. Yang, X.-L. Huang, and J.-L. Huang, “An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing,” Asian Test Symposium, 367-372, Taichun, Taiwan, Nov. 2009
  36. J.-L. Huang, X.-L. Huang, and P.-Y. Kang, “A Self-Testing Assisted Pipelined-ADC Calibration Technique,” International Conference on ASIC, Changsha, China, Oct. 2009
  37. K.-W. Yeh, M.-F. Wu, and J.-L. Huang, “A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method,” International Conference on Algorithms and Architectures for Parallel Processing, Taipei, Taiwan, Jun. 2009
  38. X.-L. Huang, Yuan-Chi Yu, and Jiun-Lang Huang, “Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC,” International Symposium on VLSI Design, Automation, and Test, HsinChu, Taiwan, Apr. 2009
  39. X.-L. Huang, Y.-C. Yu, and J.-L. Huang, “Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input,” Asia and South Pacific Design Automatic Conference, Yokohama, Japan, Jan. 2009
  40. J.-J. Huang and J.-L. Huang, “Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry,” Asian Test Symposium, Sapporo, Japan, Nov. 2008
  41. Y.-T. Lin, M.-F. Wu, and J.-L. Huang, “PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment,” Asian Test Symposium, Sapporo, Japan, Nov. 2008
  42. P.-H. Chiu and J.-L. Huang, “A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization,” International Symposium on Flexible Electronics and Displays, Hsin-Chu, Taiwan, Nov. 2008
  43. M.-F. Wu, J.-L. Huang, X. Wen, and K. Miyase, “Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing,” International Test Conference, Santa Clara, Oct. 2008
  44. X.-L. Huang, Y.-C. Yu, and J.-L. Huang, “Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs,” International Mixed-Signals, Sensors, and Systems Test Workshop, Vancouver, Canada, Jun. 2008
  45. Y.-L. Ma and J.-L. Huang, “A Self-Testing and Calibration Technique for Current-Steering DACs,” International Symposium on VLSI Design, Automation, and Test, 295-298, Hsin-Chu, Taiwan, Apr. 2008
  46. C.-Y. Huang, T.-H. Ko, and J.-L. Huang, “Design of a Fault Tolerant Carry Lookahead Adder,” International Test Synthesis Workshop, Santa Barbara, U.S.A., Apr. 2008
  47. C.-W. Lin, Jiun-Lang Huang, “A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays,” VLSI Test Symposium, San Diego, U.S.A., Apr. 2008
  48. M.-F. Wu, K.-S. Hu, and J.-L. Huang, “An Efficient Peak Power Reduction Technique for Scan Testing,” Asian Test Symposium, Beijing, Oct. 2007
  49. T.-L. Hung and J.-L. Huang, “A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing,” VLSI Test Symposium, Berkeley, California, U.S.A., May 2007
  50. J.-L. Huang, “A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter,” Asian Test Symposium, Fukuoka, Japan, Nov. 2006
  51. S.-W. Chang and J.-L. Huang, “An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing,” VLSI Design/CAD Symposium, HuaLian, Aug. 2006
  52. J.-L. Huang, “Extracting Random Jitter in the Existence of Sinusoidal Jitter,” International Mixed-Signal Testing Workshop, Edinburgh, Jun. 2006
  53. C.-Y. Kuo, and J.-L. Huang, “A period tracking based on-chip sinusoidal jitter extraction technique,” VLSI Test Symposium, 400-405, Berkeley, California, U.S.A., Apr. 2006
  54. X.-L. Huang, and J.-L. Huang, “A routability constrained scan chain ordering technique for test power reduction,” Asia and South Pacific Design Automation Conference, 648--652, Yokohama, Japan, Jan. 2006
  55. J.-L. Huang, “Random jitter testing using low tap-count delay lines,” Asian Test Symposium, 100-105, Calcutta, India, Dec. 2005
  56. J. L. Huang, “An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines,” International Mixed-Signal Testing Workshop, Cannes, France, Jun. 2005
  57. J. J. Huang and J. L. Huang, “An Infrastructure IP for On-Chip Clock Jitter Measurement,” International Conference on Conmputer Design, 186-191, San Jose, U.S.A., Oct. 2004
  58. J. J. Huang, and J. L. Huang, “A Low-Cost Jitter Measurement Technique for BIST Applications,” Asian Test Symposium, pp. 336-339, Xian, China, Nov. 2003
  59. J. J. Huang, and J. L. Huang, “A Delay-Line Based On-Chip Jitter Measurement Technique,” VLSI Design/CAD Symposium, Aug. 2003
  60. J. J. Huang, and J. L. Huang, “A Low-Cost Jitter Measurement Technique for BIST Applications,” International Mixed-Signal Testing Workshop, pp. 177-181, 2003
  61. H. C. Hong, J. L. Huang, K. T. Cheng, and C. W. Wu, “On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators,” Asian Test Symposium, 49-54, Nov. 2002
  62. Y. J. Chang, S. J. Chang, C. K. Ong, J. C. Ho, J. L. Huang, K. T. Cheng, and W. C. Wu, “A BIST Scheme for the Embedded ADC in ADSL SoC,” VLSI Design/CAD Symposium, pp. 174-177, Aug. 2002
  63. J.L. Huang and K.T. Cheng, “An on-chip short-time interval measurement technique for testing high-speed communication links,” Proc. VLSI Test Symposium, pp. 380-385, 2001
  64. J. L. Huang and K. T. Cheng, “A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits,” Proc. Asia and South Pacific Design Automation Conference, pp. 605-610, 2000
  65. J.L. Huang, C.K. Ong, and K.T. (Tim) Cheng, “A BIST Scheme for On-Chip ADC and DAC Testing,” Proc. Design, Automation & Test in Europe, pp. 216-220, 2000
  66. J. L. Huang, and K. T. Cheng, “A delta-sigma modulation based BIST scheme for mixed-signal systems,” Proc. Southwest Symposium on Mixed-Signal Design, pp. 147-152, 2000
  67. J.A. Tofte, C.K. Ong, J.L. Huang, and K.T. Cheng, “Characterization of a pseudo-random testing technique for analog and mixed-signal built-in self-test,” Proc. VLSI Test Symposium, pp. 237-246, 2000
  68. J.L. Huang and K.T. Cheng, “Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis,” Proc. International Test Conference, pp. 1021-1030, 2000
  69. J. L. Huang, C. Y. Pan, and K. T. (Tim) Cheng, “Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits,” Proc. VLSI Test Symposium, pp. 220-225, 1999

Patents:

  1. 黃炫倫、黃俊郎、林王安、康平穎, “逐次逼近暫存器類比數位轉換器及其線性度校正的方法,” 中華民國專利證書號數I454065, Sept. 2014
  2. 陳弘易、陳昶聿、黃炫倫、黃俊郎, “數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器,” 中華民國專利證書號數I434517, Apr. 2014
  3. 吳孟帆、黃俊郎、溫曉青、宮瀨紘平, “生成裝置、判別方法、生成方法及びプログラム,” 日本特許第5481754號, Feb. 2014
  4. 黃炫倫、黃俊郎、林王安、康平穎, “迴路測試架構與方法,” 中華民國專利證書號數I410051, Sept. 2013
  5. 吳孟帆、黃俊郎、溫曉青、宮瀨紘平, “測試圖案最佳化的方法,” 中華民國專利證書號數I403746, Aug. 2013
  6. Hung-I Chen, Chang-Yu Chen, Xuan-Lun Huang, and Jiun-Lang Huang, “METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME,” U.S. Patent 8,502,723, Aug. 2013
  7. Xuan-Lun Huang and Jiun-Lang Huang, “SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN,” U.S. Patent No. 8,487,794, Jul. 2013
  8. 李權哲，黃俊郎，黃瑞澤, “顯示器驅動電路之測試裝置,” 中華民國專利證書號數I375806, Nov. 2012
  9. 黃俊郎，黃瑞澤，李權哲, “類比數位轉換器,” 中華民國專利證書號數I335730, Jan. 2011
  10. Jiun-Lang Huang, Jui-Jer Huang, and Chuan-Che Lee, “Analog-to-Digital Converter,” U.S. Patent No. 7,616,147, Nov. 2009