潘正聖兼任教授的著作列表 - Publication List of Samuel C. Pan

Publication List of 潘正聖 Samuel C. Pan

Journal articles & book chapters:

  1. Cheng-Sheng Pan, K. Wu, P. Freiberger, A. Chatterjee, and G. Sery, “A scaling Methodology for Oxide-Nitride-Oxide Interpoly Dielectric for EPROM Applications,” IEEE Trans. Electron Devices, vol. 37, 1439, 1990
  2. K. Wu, Cheng-Sheng Pan, J. Shaw, P. Freiberger, and G. Sery, “A model for EPROM Intrinsic Charge Loss Mechanisms,” Proc. 28th Int. Reliab. Phys. Symp. IEEE, 145, 1990
  3. Cheng-Sheng Pan, K. Wu and G. Sery, “Physical Origin of Long-Term Charge Loss in Floating Gate EPROM with an Interpoly Oxide-Nitride-Oxide Stacked Dielectric,” IEEE Electron Device Letters, vol. 12, 51 (1991).
  4. Cheng-Sheng Pan, K. Wu, D. Chin, G. Sery, and J. Kiely,, “High Temperature Charge Loss Mechanism in Floating-Gate EPROM with an Oxide-Nitride-Oxide (ONO) Interpoly Stacked Dielectric,” IEEE Electron Device Letters, vol. 12, 506 (1991)
  5. K. Wu, S. Pan, D. Chin, and J. Shaw, “Channel Length and Width Effects on NMOS Transistor Degradation under Constant Positive Gate Voltage Stressing,” IEDM Tech. Dig., 735 (1991)
  6. S. Lee, C. Liang, Cheng-Sheng Pan, W. Lin, and J. Mark, “A study on the Physical Mechanism in the Recovery of Gate Capacitance to Cox in Implanted Polysilicon MOS Structures,” IEEE Electron Device Letters, vol. 13, 2 (1992)
  7. P. Freiberger, L. Yau, Cheng-Sheng Pan, and G. Sery, “Fabrication of Interpoly Dielectric for EPROM related Technologies,” US Patent Number 5104819, Apr. 14, 1992
  8. T. Ong, A. Fazio, N. Mielke, S. Pan, G. Atwood, and S. Lai, “Instability of Erase Threshold Voltage in ETOX Flash Memory Array,” presented in SRC Nonvolatile Workshop in Berkeley, Oct. 1992
  9. A. Brand, K. Wu, S. Pan and D. Chin, “Novel Read Disturb Failure Mechanism Induced by Flash Cycling,” Proc. 31th Int. Reliab. Phys. Symp. IEEE, 127 (1993)
  10. D. Chin, S. Pan, and K. Wu, “Geometry Effect on CMOS Transistor Stability under Gate Bias Stress,” Proc. 31th Int. Reliab. Phys. Symp. IEEE, 66 (1993)
  11. U. Mitra, S. Rajagopalan, S. Pan, C. Lin, K. Gupta, G. Neubauer, S.Mittal, G. Sery, K. Hassergian and W. Lo, “Reaction of DI water with Si and its Effect on Gate Oxide Integrity,” Proc. 31th Int Reliab. Phys. Symp. IEEE, 28 (1993)
  12. T. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, and S. Lai, “Erratic Erase in ETOX Flash Memory Array,” VLSI Technology Symposium, Kyoto 1993
  13. W.J. Tsai, N.K. Zous, C.J. Liu, C.C. Liu, C.H. Chen, T. Wang, S. Pan and C.Y. Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” IEDM Tech. Dig., 719 (2001)
  14. S.L. Lung, C.L. Liu, S.S. Chen, S.C. Lai, C.W. Tsai, T.T. Sheng, Tanhui Wang ,Sam Pan, T.B. Wu, Rich Liu, “Low Temperature Epitaxial Growth of PZT on Conductive Perovskite LaNiO, Electrode for Embedded Capacitor-Over-Interconnect (COI) FeRAM Application,” IEDM Tech. Dig., 275 (2001)
  15. W.J. Tsai, S.H. Gu, N.K. Zous, C.C. Yeh, C.C. Liu, C.H. Chen, T. Wang, S. Pan and C.Y. Lu, “Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell,” 40th Int. Reliab. Phys. Symp. IEEE, 34 (2002)
  16. T. Luoh, C.S. Chen, L.W. Yang, H.H. Shih, K.C. Chen, C. Hsueh, H. Chung, S. Pan and C.Y. Lu, “Stress Release for Shallow Trench Isolation by Single-Wafer, Rapid-Thermal Steam Oxidation,” 10th IEEE International Conference on Advanced Thermal Processing of Semiconductors –RPT, 111 (2002)
  17. S. Pan, C.C. Yeh, R. Liu and C.Y. Lu, “Nonvolatile Memory Challenges toward Gigabit Era and a Nano-scale Flash Cell: PHINES,” SSDM Extended Abstracts, 152 (2002)
  18. T.H. Fan, T.C. Lu, Sam Pan, “New Spider-Webs Test Structure and Characterization Methodology for Flash Memory Tunnel Oxide Quality,” Proc. IEEE 2002 Int. Conference on Microelectronic Test Structures, vol. 15, 133 (2002)
  19. W.J. Tsai, C.C. Yeh, N.K. Zous, C.C. Liu, S.K. Cho, C.H. Chen, T. Wang S. Pan and C.Y. Lu, “Hot Carrier Enhanced Read Disturb and Scaling Effects in a Localized Trapping Storage SONOS Type Flash Memory Cell,” SSDM Extended Abstracts, 164 (2002)
  20. T.H. Fan, C.C. Yeh, T.C. Lu and S. Pan, “A Novel Soft-Program Scheme for More Than 2 Bits Multi-Level Cell Flash Design,” SSDM Extended Abstracts, 610 (2002)
  21. C.C. Yeh, W.J. Tsai, M.I. Liu, T.C. Lu, S.K. Cho, C.J. Lin, T. Wang, S. Pan and C.Y. Lu, “PHINES: a Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” EDM Tech. Dig., 931(2002)
  22. C.C. Yeh, W.J. Tsai, T.C. Lu, S.K. Cho, T. Wang, S. Pan, C.Y. Lu, “A Modified Read Scheme to Improve Read Disturb and Second Bit Effect in a Scaled MXVAND Flash Memory Cel,” IEDM Tech. Dig., 931(2002)
  23. C.C. Yeh, W. Tsai, T. Lu, H. Chen, H. Lai, N. Zous, Y. Liao, G. You, S. Cho, C. Liu, F. Hsu, L. Huang, W. Chiang, C. Liu, C. Cheng, M. Chou, C. Chen, Tahui Wang, Wenchi Ting, Sam Pan, Jo. Ku, and C.Y. Lu, “Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory,” IEDM Tech. Dig., 173 (2003)
  24. T. Wang, W. Tsai, S. Gu, C. Chan, C. Yeh, N. Zous, T. Lu, Sam Pan and C.Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells,” IEDM Tech. Dig., 169 (2003)
  25. H. Lai, N. Zous, W. Tsai, T. Lu, Tahui Wang, Y. King, and Sam Pan, “Reliable Extraction of Interface States from Charge Pumping Method in Ultra-Thin Gate Oxide MOSFET's,” Proc. IEEE 2002 Int. Conference on Microelectronic Test Structures, ICMTS, 99 (2003)
  26. K. Chen, H. Shih, Y. Hwang, C. Hsueh, H. Chung, Sam Pan, and C,Y, Lu, “Applications of Single-Wafer Rapid-Thermal Processing to the Manufacture of Advanced Flash Memory,” IEEE Trans. Semiconductor Manufacturing, vol., 16, 128 (2003)
  27. T. Luoh, T. Han, Y. Yang, K. Chen, H. Shih, Y. Hwang, C. Hsueh, H. Chung, Sam Pan, and C.Y. Lu, “Single-Wafer Polysilicon Engineering for the Improvement of Over Erase in a 0.18-m Floating-Gate Flash Memory,” IEEE Trans. Semiconductor Manufacturing, vol., 16, 155 (2003)
  28. S. Hsu, T. Wang, H. Shih, K. Chen, Y. Hwang, C. Hsueh, H. Chung, Sam Pan, and C.Y. Lu, “Applications of Single-Wafer Thermal Processing to 0.15-m High-Density MROM,” IEEE Trans. Semiconductor Manufacturing, vol., 16, 147 (2003)
  29. N. Zous, Y. Chen, C. Chin, W. Tsai, T, Lu, M. Chen, W. Lu, Tahui Wang, Samuel C. Pan, and C.Y. Lu, “An Endurance Evaluation Method for Flash EEPROM,” IEEE Trans. Electron Devices, vol., 51, 720 (2004)
  30. C. H Lai, M. H. Liu, S. Su, T. C. Lu and S. Pan, “A Novel Gate-Coupled SRC ESD Protection Structure with High Latchup Immunity for High-Speed I/O Pad,” IEEE Electron Device Letters, vol. 25, 328 (2004)
  31. W. Tsai, C. Yeh, N. Zous, C. Liu, S. Cho, Tahui, Wang, Samuel C. Pan, C.Y. Lu, “Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell,” IEEE Trans. Electron Devices, vol., 51, 434 (2004)
  32. Y. Chang, T. Lu, Sam Pan, C.Y. Lu, “Modeling for the 2nd-Bit Effect of a Nitride-Based Trapping Storage Flash EEPROM Cell Under Two-Bit Operation,” IEEE Electron Device Letters, vol., 25, 95 (2004)
  33. C. Lai, M. Liu, S. Su, T. Lu, and Sam Pan, “A Novel Gate-Coupled SCR ESD Protection Structure With High Latchup Immunity for High-Speed I/O Pad,” IEEE Electron Device Letters, vol., 25, 328 (2004)
  34. C. C. Cheng, K. C. Tu, Tahui Wang, T. H. Hsieh, J. T. Tzeng, R.S. Liou, Sam Pan, and S. L. Hsu, “Investigation of Hot Carrier Degradation Modes in LDMOS by Using a Novel Three-Region Charge Pumping Technique, 44th Int. Reliability Phys. Symp,” IEEE, 334 (2006)
  35. C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and Characterization of Various Hot-Carrier Degradation Modes in LDMOS by using a Three-Region Charge Pumping Technique,” IEEE Trans. Device and Materials Reliability, vol. 6, 358 (2006)
  36. Doong, K.Y.Y.; Keh-Jeng Chang; Lin, S.-C.; Tseng, H.C.; Dagonis, A.; Pan, S, “4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model,” IEEE International Conference on Microelectronic Test Structures (ICMTS) (2009)
  37. Tseng-Chin Luo; Chao, M.C.-T.; Wu, M.S.-Y.; Kuo-Tsai Li; Hsia, C.C.; Huan-Chi Tseng; Chuen-Uan Huang; Yuan-Yao Chang; Pan, S.C.; Young, K.K.-L, “A novel array-based test methodology of local process variation monitor,” ITC (2009)
  38. Tseng-Chin Luo; Chao, M.C.-T.; Wu, M.S.-Y.; Kuo-Tsai Li; Hsia, C.C.; Huan-Chi Tseng; Fisher, P.A.; Chuen-Uan Huang; Yuan-Yao Chang; Pan, S.C.; Young, K.K.-L, “A novel array-based test methodology of local process variation monitor,” IEEE Trans. Semiconductor Manufacturing, vol. 24 , 280 (2011)
  39. Jing Ye; Yu Huang; Yu Hu; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li; Weipin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; Kartik K. Kumara; Charles Liu; Sam Pan, “Diagnosis and Layout Aware (DLA) Scan Chain Stitching,” International Test Conference (ITC), 1 (2013)
  40. Po-Hao Tseng, Wei-Cheng Tian, Samuel C. Pan and Jenn-Gwo Hwu, “Formation of Single Crystal Si-Nanowire by Electric Field Self-Redistribution Effect in Anodic Oxidation for Multilayer Array Application,” IEEE Trans. Nanotechnology, vol. 13, 1084 (2014)
  41. Jing Ye; Yu Huang; Yu Hu; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li; Weipin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; Kartik K. Kumara; Charles Liu; Sam Pan, “Diagnosis and Layout Aware (DLA) Scan Chain Stitching,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, issue 3, 466 (2015)