Publication List of 張耀文 Yao-Wen Chang

Journal articles & book chapters:

  1. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, “Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. (TCAD), Vol. 27, No. 4, Apr. 2008
  2. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “Effective wire models for X-architecture placement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 4, Apr. 2008
  3. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, “A new multilevel framework for large-scale interconnect-driven floorplanning,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 2, Feb. 2008
  4. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, “Full-chip routing considering double-via insertion,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, 2008
  5. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: an analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, 2008
  6. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation,” ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 3, No. 3, 32 pages, Nov. 2007
  7. B.-Y. Su and Y.-W. Chang, “An exact jumper insertion algorithm for antenna avoidance/fixing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 10, pp. 1818--1829, Oct. 2007
  8. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “Temporal floorplanning using the three-dimensional transitive closure sub-graph,” ACM Trans. Design Automation of Electronic Systems, Vol. 12, No. 4, 34 pages, Sept. 2007
  9. K. S.-M. Li, Y.-W. Chang, C.-L. Lee, C.-C. Su, and J. E Chen,, “Multilevel full-chip routing with testability and yield enhancement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 9, pp. 1625--1636, Sept. 2007
  10. J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang,, “A network-flow based RDL routing algorithm for flip chip design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1417--1429, Aug. 2007
  11. H.-C. Lee, Y.-W. Chang, and H. Yang, “MB*-tree: A multilevel floorplanner for large-scale building-module design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1430--1444, Aug. 2007
  12. T.-C. Chen and Y.-W. Chang, “Multilevel full-chip gridless routing with applications to optical proximity correction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 6, pp. 1041--1053, Jun. 2007
  13. B.-Y. Su, Y.-W. Chang, and J. Hu, “An exact jumper insertion algorithm for antenna violation avoidance/fixing considering routing obstacles,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, 719--734, Apr. 2007
  14. C.-W. Liu and Y.-W. Chang, “Power/ground network and floorplan co-synthesis for fast design convergence,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 4, pp. 693—704, Apr. 2007
  15. K. S.-M. Li, C.-C. Su, Y.-W. Chang, C.-L. Lee, and J. E Chen, “P1500 Standard Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, 2513--2525, Nov. 2006
  16. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC coupling-aware simulation and on-chip bus encoding for delay reduction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 10, 2258—2264, Oct. 2006
  17. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel Routing with Jumper Insertion for Antenna Avoidance,” Integration: The VLSI Journal, Vol. 39, Issue 4, pp. 420--432, Jul. 2006
  18. T.-C. Chen and Y.-W. Chang, “Modern Floorplanning Based on B*-trees and Fast Simulated Annealing,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 4, 637—650, Apr. 2006
  19. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,, “Reliable crosstalk-driven interconnect optimization,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 11, No. 1, 88—103, Jan. 2006
  20. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, “Multilevel full-chip routing considering crosstalk and performance,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 6, pp. 869--878, Jun. 2005
  21. J.-M. Lin and Y.-W. Chang, “TCG: A transitive closure graph based representation for general floorplans,” IEEE Transactions on VLSI Systems, Vol. 13, No. 4, 288--292, Apr. 2005
  22. G.-M. Wu, C.-T. M. Chao, and Y.-W. Chang,, “A clustering and probability based partitioning algorithm for time-multiplexed FPGAs,” Integration: The VLSI Journal., Vol. 38, Issue 2, pp. 245—265, Dec. 2004
  23. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, 968—980, Jul. 2004
  24. Y.-W. Chang and S.-P. Lin, “MR: A New Framework for Multilevel Full-Chip Routing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, 793—800, May 2004
  25. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, K.-Y. Chao, “Simultaneous floorplanning and buffer block planning,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, 694—703, May 2004
  26. G.-M. Wu, M. Shyu, and Y.-W. Chang, “Universal switch blocks for three-dimensional FPGA design,” IEE Proceedings---Circuits, Devices, and Systems, Vol. 151, No. 1, 49—57, Feb. 2004
  27. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, “Timing modeling and optimization under the transmission line model,” IEEE Transactions on VLSI Systems, Vol. 12, No. 1, pp. 28--41, Jan. 2004
  28. J.-M. Lin, Y.-W. Chang, and S.-P. Lin,, “Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme,” IEEE Transactions on VLSI Systems (TVLSI),, Vol. 11, No. 4,, pp. 679--686,, Aug. 2003
  29. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,, “Rectilinear block placement using B*-trees,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 8., No. 2,, pp. 188-202,, Apr. 2003
  30. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, T.-C. Chen, and J.-Y. Jou,, “Inductance modeling for on-chip interconnects,” Analog Integrated Circuits and Signal Processing Journal,, Vol. 35, No 1,, pp. 65-78,, Apr. 2003
  31. Y.-W. Chang, K. Zhu, G.-M. Wu, D. F. Wong, G.-M. Wu, and C. K. Wong,, “Analysis of FPGA/FPIC switch modules,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 8, No. 1,, pp. 11-37, Jan. 2003
  32. J.-M. Lin, H.-L. Lin, and Y.-W. Chang,, “Arbitrarily shaped rectilinear module packing using TCG,” IEEE Trans. on VLSI Systems (TVLSI),, Vol. 10, No. 6,, pp. 886-901,, Dec. 2002
  33. Y.-M. Lee, C.-P. Chen, Y.-W. Chang, and D.-F. Wong,, “Simultaneous buffer-sizing and wire-sizing for clock trees based on Lagrangian relaxation,” VLSI Design,, Vol. 15, No. 3,, pp. 587--594,, Nov. 2002
  34. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Performance-driven placement for dynamically reconfigurable FPGAs,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 7, No. 4,, pp. 628-642,, Oct. 2002
  35. J.-M. Lin, H.-E. Yi, and Y.-W. Chang, “Module placement with boundary constraints using B*-trees,” IEE Proceedings--Circuits, Devices and Systems,, Vol. 149, No. 4,, pp. 251--256,, Aug. 2002
  36. H. Fang, Y.-L. Wu, and Y.-W. Chang,, “Comments on “Generic universal switch blocks,” IEEE Trans. on Computers (TC),, Vol. 51, No. 1,, pp. 93—95,, 2002
  37. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Generic ILP-based approaches for time-multiplexed FPGA partitioning,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 20, No. 10,, pp. 1266—1274,, Oct. 2001
  38. Y.-W. Chang, J.-M. Lin, and D. F. Wong,, “A matching-based algorithm for FPGA channel segmentation design,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 20, No. 6,, pp. 784-791,, Jun. 2001
  39. H.-R. Jiang, Y.-W. Chang, and J.-Y. Jou,, “Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 19, No. 9,, pp. 999--1010,, Sept. 2000
  40. Y.-W. Chang, K. Zhu, and D. F. Wong,, “Timing-driven routing for symmetrical-array-based FPGAs,',” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 5, No. 3,, pp. 433-450,, Jul. 2000
  41. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,, “Generic universal switch blocks,” IEEE Trans. on Computers (TC),, vol. 49, no. 4,, pp. 348-359,, Apr. 2000
  42. G.-M. Wu and Y.-W. Chang, “Quasi-universal switch matrices for FPD design,” IEEE Trans. on Computers (TC), Vol. 48, No. 10,, pp. 1107-1122, Oct. 1999

Conference & proceeding papers:

  1. W.-P. Lee, H.-Y. Liu, K.-H. Ho, and Y.-W. Chang, “Sensitivity-Based Multiple-Vt Cell Swapping for Leakage Power Reduction Under Timing Requirements,” Proceedings of The 4th IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2008), Hsinchu, Taiwan, Apr. 2008
  2. T.-C. Chen, M. Cho, D. Z. Pan and Y.-W. Chang, “Metal-Density Driven Placement for CMP Variation and Routability,” Proceedings of ACM International Symposium on Physical Design (ISPD-2008), Portland, Oregon, Apr. 2008
  3. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “BioRoute: A network flow based routing algorithm for digital microfluidic biochips,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  4. H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, “Novel wire density driven full-chip routing for CMP variation control,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  5. C.-W. Lin. S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, “Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  6. I.-J. Lin and Y.-W. Chang, “An efficient algorithm for statistical circuit optimization using Lagrangian relaxation,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  7. Y.-P. Chen, J.-W. Fang, and Y.-W. Chang, “ECO timing optimization using spare cells and technology remapping,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  8. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “An ILP algorithm for post-floorplanning voltage-island generation,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  9. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, “Lithography-aware routing with predictive OPC formulae,” The 18th VLSI Design/CAD Symposium, Hua-Lien, Aug. 2007
  10. H.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “A high quality transitive-closure-graph-based macro placer,” The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007
  11. C.-F. Li, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, “Post-placement leakage optimization for partially dynamically reconfigurable FPGAs,” Proceedings of IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED-07), Aug. 2007
  12. P-H. Yuh, C.-L. Yang, and Y.-W. Chang, “Placement of digital microfluidic biochips using the T-tree formulation,” /IEEE Design Automation Conference (DAC-2006), pp. 931--934, San Francisco, CA, Jul. 2007
  13. H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, “A provably good approximation algorithm for power optimization using multiple supply voltages,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  14. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu, “MP-trees: a packing-based macro placement algorithm for mixed-size designs,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  15. J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer linear programming algorithm for flip-chip routing,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  16. Z.-W. Jiang, H.-C. Chen, T.-C. Chen, and Y.-W. Chang, “Challenges and solutions in modern VLSI placement,” Proceedings of The 3rd IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2007), pp. 111--115, Hsinchu, Taiwan, Apr. 2007
  17. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, “Efficient obstacle-avoiding rectilinear Steiner tree construction,” Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 127--134, Austin, TX, Mar. 2007
  18. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “X-architecture placement based on effective wire models,” Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 87--94, Austin, TX, Mar. 2007
  19. I.-J. Lin, T.-Y. Lin, and Y.-W. Chang, “Statistical circuit optimization considering device and interconnect process variations,” Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2007), Austin, TX, Mar. 2007
  20. C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, “Recent research and emerging challenges in physical design for manufacturability/reliability,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2007), pp. 238--243, Yokohama, Japan, Jan. 2007
  21. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “A high quality analytical placer considering preplaced blocks and density constraint,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 187--192, San Jose, CA, Nov. 2006
  22. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “Voltage island aware floorplanning for power and timing optimization,” /ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 389--394, San Jose, CA, Nov. 2006
  23. H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, Y.-W. Chang, and S.-Y. Kuo, “Current path analysis for electrostatic discharge protection,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 510--515, San Jose, CA, Nov. 2006
  24. Z.-W. Jiang and Y.-W. Chang, “An optimal simultaneous diode/jumper insertion algorithm for antenna fixing,” /ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 669--674, San Jose, CA, Nov. 2006
  25. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, “Novel full-chip gridless routing considering double-via insertion,” ACM/IEEE Design Automation Conference (DAC-2006), pp. 755--760, San Francisco, CA, Jul. 2006
  26. C.-Y. Lai, S.-K. Jeng, Y.-W. Chang, and C.-C. Tsai,, “Surface integral inductance extraction for general interconnect structures,” International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, May 2006
  27. C.-W. Liu and Y.-W. Chang, “Floorplan and power/ground network co-synthesis for fast design convergence,” ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, Apr. 2006
  28. B.-Y. Su, Y.-W. Chang, and J. Hu, “An optimal jumper insertion algorithm for antenna effect avoidance/fixing on general routing trees with obstacles,” ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, Apr. 2006
  29. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace2: a hybrid placer using partitioning and analytical techniques,” ACM International Symposium on Physical Design (ISPD-2006),, San Jose, CA, Apr. 2006
  30. Y.-W. Lin and Y.-W. Chang, “Thermal-driven interconnect optimization by gate and wire sizing,” The IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2006), pp. 151--154, Hsinchu, Taiwan, Apr. 2006
  31. C.-Y. Peng, W.-C. Chao, Y.-W. Chang, and J.-H. Wang, “Simultaneous block and I/O buffer floorplanning for flip-chip design,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 213--218, Yokohama, Japan, Jan. 2006
  32. K. S.-M. Li, Y.-W. Chang, C.-C. Su, C.-L. Lee, and J. E. Chen, “P1500 based interconnect diagnosis for delay and crosstalk faults,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 366--371, Yokohama, Japan, Jan. 2006
  33. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, “A novel framework for multilevel full-chip gridless routing,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 636--641, Yokohama, Japan, Jan. 2006
  34. B.-Y. Su and Y.-W. Chang, “An exact jumper insertion algorithm for antenna effect avoidance/fixing,” Proc. of ACM/IEEE Design Automation Conference (DAC-2005), Anaheim, CA, Jun. 2005
  35. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, “Multilevel full-chip routing for the X-based architecture,” Proc. of ACM/IEEE Design Automation Conference (DAC-2005), Anaheim, CA, Jun. 2005
  36. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, May 2005
  37. T.-C. Chen and Y.-W. Chang, “Modern floorplanning based on fast simulated annealing,” Proceedings of ACM International Symposium on Physical Design (ISPD-2005), San Francisco, CA, Apr. 2005
  38. T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y.-W. Chang, “NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs,” Proceedings of ACM International Symposium on Physical Design (ISPD-2005), San Francisco, CA, Apr. 2005
  39. S.-M Lee, C.-W. Lee, Y.-W. Chang, C.-C. Su, and J.-Y. Chen, “Multilevel full-chip routing with testability and yield enhancement,” Proceedings of ACM Interational Workshop on System Level Interconnect Prediction (SLIP-2005), San Francisco, CA, Apr. 2005
  40. S.-L. Wang and Y.-W. Chang, “Delay modelling for buffered RLC/RLY trees,” Proceedings of The 1st IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2005), Hsinchu, Taiwan, Apr. 2005
  41. T.-C. Chen and Y.-W. Chang, “Multilevel gridless routing considering optical proximity effects,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  42. J.-Y. Wuu, T.-C. Chen, and Y.-W. Chang, “SoC test scheduling using the B*-tree based flooprlanning technique,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  43. G.-M. Wu, J.-M. Lin, Y.-W. Chang, and R.-H. Chuang, “Placement with symmetry constraints for analog layout design,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  44. J.-M. Hsu and Y.-W. Chang, “A reusable methodology for non-slicing floorplanning,” Proceedings of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, Dec. 2004
  45. P.-H. Yu, C.-L.Yang and Y.-W. Chang, “Temporal floorplanning using the T-tree formulation,” Proceedings of IEEE/ACM International Conference on computer-Aided Design (ICCAD-2004), San Jose, CA, Nov. 2004
  46. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with jumper insertion for antenna avoidance,” Proceedings of IEEE International SOC Conference (SOC-2004), Santa Clara, California, Sept. 2004
  47. M.-C. Wu and Y.-W. Chang, “Placement with Alignment and Performance Constraints Using the B*-tree representation,” Proceedings of IEEE International Conference on Computer Design (ICCD-2004), San Jose, CA, Sept. 2004
  48. S.-W. Wu and Y.-W. Chang, “Efficient power/ground network analysis for power integrity driven design methodology,” Proc. of ACM/IEEE Design Automation Conference (DAC-2004), San Diego, CA, Jun. 2004
  49. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC effects on worst-case switching patterns for on-chip buses,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004
  50. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with antenna avoidance,” Proceedings of ACM International Symposium on Physical Design (ISPD-2004), Phoenix, Arizona, Apr. 2004
  51. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “Layout techniques for for on-chip interconnect inductance reduction,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 269-273, Yokohama, Japan, Jan. 2004
  52. Y.-H. Cheng and Y.-W. Chang, “Integrating buffer planning with floorplanning for simultaneous multi-objective Optimization,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 624--627, Yokohama, Japan, Jan. 2004
  53. P.-H. Yu, C.-L.Yang, Y.-W. Chang, and H.-L. Chen, “Temporal floorplanning using 3D-subTCG,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 725--730, Yokohama, Japan, Jan. 2004
  54. T. -Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee,, “A fast crosstalk- and performance-driven multilevel routing system,”,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),, pp. 382--387,, San Jose, Nov. 2003
  55. H.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang,, “Multilevel floorplanning/placement for large-scale modules using B*-trees,” Proceedings of ACM/IEEE Design Automation Conference (DAC),, pp. 812--817,, Anaheim, CA, Jun. 2003
  56. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao,, “Simultaneous Floorplanning and Buffer Block Planning,”,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 431-434,, Kitakyushu, Japan,, Jan. 2003
  57. S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, “, “Noise-aware buffer planning for interconnect-driven floorplanning,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 423-426,, Kitakyushu, Japan, Jan. 2003
  58. J.-M. Lin, S.-R. Pan, and Y.-W. Chang,, “Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 851-854, Kitakyushu, Japan, Jan. 2003
  59. S.-P. Lin and Y.-W. Chang,, “A novel framework for multilevel routing considering routability and performance,”,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),, pp. 44-50, San Jose,, Nov. 2002
  60. J.-M. Lin and Y.-W. Chang, “, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” Proceedings of ACM/IEEE Design Automation Conference (DAC),, New Orleans,, Jun. 2002
  61. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen,, “On-chip inductance modeling for coplanar interconnects,” Proceedings of the IEEE Symposium on Circuits and Systems (ISCAS-2002), Pheonix, AZ, May 2002
  62. C.-Y. Chang, H.-R. Jiang, and Y.-W. Chang,, “Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning,” Proceedings of the 2002 IEEE International Symposium on Quality of Electronic Design (ISQED),, San Jose, CA,, Mar. 2002
  63. J.-M. Lin, H.-L. Lin, and Y.-W. Chang,, “Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,” Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE),, pp. 69-75, Paris, France,, Mar. 2002
  64. G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,, “Generic ILP-based partitioning algorithms for dynamically reconfigurable FPGAs,”,” Generic ILP-based partitioning algorithms for dynamically reconfigurable FPGAs,”, pp. 335-340,, Austin, TX, Sept. 2001
  65. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Precedence-constrained placement for dynamically reconfigurable FPGAs,” Proceedings of the 2001 IEEE International Conference on Computer Design (ICCD),, pp. 501-504,, Austin, TX, Sept. 2001
  66. T.-C. Chen, S.-R. Pan, and Y.-W. Chang,, “Performance optimization by wire/buffer sizing under the transmission line model,” Proceedings of the 2001 IEEE International Conference on Computer Design (ICCD),, pp. 192-197,, Austin, TX,, Sept. 2001
  67. J.-M. Lin and Y.-W. Chang,, “TCG: A transitive closure graph-based representation for non-slicing floorplans,” Proceedings of the 38th ACM/IEEE Design Automation Conference (DAC), pp. 764-769,, Las Vegas, NV,, Jun. 2001
  68. S.-R. Pan and Y.-W. Chang,, “Crosstalk-constrained performance optimization by using wire sizing and perturbation,”,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 581-584,, Austin, TX,, Sept. 2000
  69. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,, “Rectilinear block placement using B*-trees,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 351-356, Austin, TX,, Sept. 2000
  70. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu,, “B*-trees: A new representation for non-slicing floorplans,” Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC),, pp. 458-463,, LA, CA,, Jun. 2000
  71. Y.-W. Chang and Y.-T. Chang,, “An architecture-driven simultaneous placement and routing for FPGAs,” Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC, pp. 567-572,, LA, CA, Jun. 2000
  72. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,, “Reliable crosstalk-driven interconnect optimization,” in Proceedings of ACM International Symposium on Physical Design (ISPD),, pp. 128-133, San Diego, CA,, Apr. 2000
  73. C.-T. M. Chao, G.-M. Wu, H.-R. Jiang, and Y.-W. Chang,, “A clustering- and probability-based algorithm for time-multiplexed FPGA partitioning,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), , pp. 364-368, San Jose, CA, Nov. 1999
  74. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,, “Generic universal switch-block architecture and its interaction with routing,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 311-314,, Austin, TX,, Oct. 1999
  75. H.-R. Jiang, J.-Y. Jou, and Y.-W. Chang,, “Noise-constrained performance optimization by simultaneous wire and gate sizing based on Lagrangian relaxation,”,” Proceedings of the 36th ACM/IEEE Design Automation Conference (DAC9), pp. 90-95,, New Orleans, LA, Jun. 1999
  76. G.-M. Wu, M. Shyu, and Y.-W. Chang, “Three-dimensional universal switch modules,” Field Programmable Gate Arrays (FPGA), Monterey, CA,, Feb. 1999

Books:

  1. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng (editors), “Electronic Design Automation: Synthesis, Verification, and Testing,” Elsevier/Morgan Kaufmann, 2008
  2. T.-C. Chen and Y.-W. Chang, “Packing floorplan representation,” Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, 2007
  3. F. Y. Young, C.-K. Koh, and Y.-W. Chang, “Buffer planning,” Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, 2007
  4. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs,” G.-J. Nam and J. Cong, Editors, 2007
  5. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “ Full-chip Nanometer Routing Techniques,” Springer, 2007
  6. Y.-W. Chang, D. F. Wong, and C. K. Wong, “Programmable logic arrays,” ncyclopedia of Electrical and Electronics Engineering (John G. Webster, Editor), John Wiley & Sons, Vol. 17, p pages, 1999

other:

  1. 陳泰蓁, 張耀文, “IC實體設計自動化所面臨的挑戰,” Jun. 2003, 零組件雜誌, pp. 68-74
  2. 張耀文, “在晶片平面規劃階段的電源/接地網合成,” Feb. 2003, 新電子月刊, 12頁
  3. 張耀文, 江蕙如, 周景楊, “拉式鬆綁法在電路最佳化之應用,” Sept. 2001, 工程科技通訊, 國科會, pp. 130-133