Publication List of 李建模 Chien-Mo Li

Journal articles & book chapters:

  1. J. C.-M. Li, P.-C. Lin, P.-C. Chiang, C.-M. Pan and C.W. Tseng, “Effective and Economic Phase Noise Testing for Single-Chip TV Tuners,” IEEE Trans. on Instrumentation and Measurement, Vol.57, No. 10, pp2265-2272, 2008
  2. Y. Huang, R Guo, W.T. Cheng, and J. C.-M. Li,, “Survey of Scan Chain Diagnosis,” IEEE Design & Test of Computers,, Vol. 25, NO. 3, pp.240-248,, 2008
  3. W.S. Chuang, James C.-M. Li, “Diagnosis of Multiple Scan Chain Timing Fault,” IEEE Trans. Computer-aided Design of IC and Syst., Vol. 27, No.6, pp.1104-1116, 2008
  4. H.T. Lin and J. C.M. Li, “Simultaneous capture and shift power reduction test pattern generator for scan testing,” IET Computers & Digital Techniques,, Volume: 2, No. 2 pp.: 132-141, March, 2008
  5. Chun-Yi Lee, James C.-M. Li, “Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing,” Journal of Low Power Electronic, Vol. 3, NO.2, 206-216, Aug. 2007
  6. J. C.-M. Li, Hung-Mao Lin and Fang Min Wang, “Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis,” IEEE Trans. Computers, Vol56, NO3, 402-414, Mar. 2007
  7. Li, J. C.-M. and E. J. McCluskey, “Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC,” IEEE Trans. on Computer-Aided Design, Nov. 2005
  8. Li, J. C. M., “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, 54, 1467-1472, Nov. 2005
  9. Li, J. C.-M., “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains,” IEEE Trans. on VLSI Systems, Vol.13, No. 6, Jun. 2005
  10. Li, J. C.-M., “Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol. E88-A, No.4, pp. 1024-1030, Apr. 2005
  11. Li, J. C. M., “A Design for Testability Technique for Low Power Delay Fault Testing,” IEICE Trans. on Electronics, Apr. 2004

Conference & proceeding papers:

  1. G-M. Chiu and J. Li, “IEEE 1500-compatible Secure Test Wrapper for Embedded IP Cores,” IEEE Int’l Test Conf., PO#4, 2008
  2. Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chih-Mou Tseng, “Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise,,” Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, PO#22, 2008
  3. W-C. Liu, J. Li, W-L. Tsai, H-T. Lin,, “Diagnosis of Logic-to-Chain Bridging Faults,” IEEE Int’l Test Conf., PO#16, 2008
  4. Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte, “On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs,” IEEE Int’l Symp. Proc. Defect and Fault Tolerant in VLSI Systems, 2008
  5. P.-C. Lin, C.-H. Hsu, J. C.-M. Li, C.-M. Chiang, and C.-J. Pan,, “Phase Noise Testing of Single Chip TV Tuners,,” IEEE VLSI-DAT, 2008
  6. C.Y. Lee, H.M. Lin, F.M. Wang, and J. C. M. Li, “Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies,” IEEE Asian South Pacific Design Automation Conference (ASP-DAC), Jan. 2007
  7. B.-H. Chen, Wei-Chuang Kao, Bin-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li, “Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique,” IEEE Asian Test Symposium, 2007
  8. Y. L Kao, W. S. Chuang, and J. C. M Li, “Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis,” IEEE Int'l Test Conf., Santa Clara, Oct. 2006
  9. Yu-Long Kao, Wei-Shun Chuang and J. C.-M. Li, “Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique,” IEEE International Test Conference, Oct. 2006
  10. H.M. Lin and J. C. M. Li, “Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains,” Proc. IEEE Int’l Test Conf., paper 42.3, Oct. 2005
  11. H.M. Lin and J. C. M. Li, “Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains,” IEEE International Test Conference, Oct. 2005
  12. M.H. Chiu and J. C. M Li, “Jump Scan: A DFT Technique for Low Power Testing,,” Proc. IEEE VLSI Test Symposium, pp. 277-282, May 2005
  13. Lee, C-Y and Li, C-M, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” Asia Solid-State Circuit Conference (ASSCC), Taiwan, 2005
  14. C.Y. Lee and J. C. M. Li, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” IEEE Asian Solid State Circuit Conf., 2005
  15. M.H. Chiu and J. C. M Li, “Jump Scan: A DFT Technique for Low Power Testing,” IEEE VLSI Test Symp., 2005
  16. E. J. McCluskey, A. Alyamani, J. C. M. Li, C. W. Tseng, E. Volkerink, F. F. Feriani, E. Li and S. Mitra, “ELF-Murphy Data on Defects and Test Sets,” Proc. IEEE VLSI Test Symposium, pp. 16-22, 2004
  17. L. W. Ko and C.M. Li, “Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique,” VLSI/CAD Symposium, pp.55, 2004
  18. C. K. Yo and C.M. Li, “Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation Patterns,” VLSI/CAD Symposium, pp.94, 2004
  19. Li, J. C.M. and E. J. McCluskey, “Diagnosis for Sequence Dependent Chips,” Proc. IEEE VLSI Test Symposium, pp.187-192, 2002
  20. C.W.Tseng, J.C.M. Li and E. J. McCluskey, “” Experimental Results for Slow Speed Testing,”,” IEEE VLSI Test Symposium, 2002
  21. Mitra, S., C.W. Tseng, J. C. M Li, and E. J. McCluskey, “Pseudo Random Testing Theoretical Models vs. Real Data,” IEEE International Workshop on Test Resource Partitioning, 2001
  22. Li, J. C.M., Tseng, C.W. and E.J. McCluskey, “Testing for Resistive and Stuck Opens,” Proc. International Test Conference, pp. 1049-1058, 2001
  23. Li, J. C.M. and E.J. McCluskey, “Diagnosis of Tunneling Opens,” Proc. IEEE VLSI Test Symposium, pp.22-27, 2001
  24. Li, J. C.M and E.J. McCluskey, “Testing for Tunneling Opens,” Proc. International Test Conference, pp. 85-94, 2000

Books:

  1. Wang, Wu, Wen and et. al., “VLSI Test Principles and Architectures,” Morgan Kaufmann, USA, 800 pages, 2006, ISBN:ISBN-10: 0123705975 and ISBN-13: 978-0123705976

Patents:

  1. 邱銘豪 李建模, “跳躍式掃描: 低功率可測試設計,” 中華民國專利 (專利號265293), Dec. 2006