汪重光教授的個人資料 - Profile of Chorng-Kuang Wang

汪重光 Chorng-Kuang Wang

國立臺灣大學電機工程學系 教授
Professor, Department of Electrical Engineering, National Taiwan University

主要研究領域:

類比射頻超大型積體電路、混合式系統超大型積體電路

Major Research Areas:

Analog RF VLSI Circuit Design, Mixed-Mode System VLSI Circuit Design

研究領域摘要:

主要研究之領域包括了類比射頻超大型積體電路與混合式系統超大型積體電路之設計。其研究之主題與成果有生醫晶片設計製作、CMOS 60-80GHz無線通訊系統射頻前端電路設計製作、CMOS LCD Driver電路設計、Conitive Radio系統前端電路設計、UWB系統之寬頻放大器設計與製作、Impulse Radio系統之時序只恢復電路之設計與製作、VDSL之SCM/DMT模式發射接收機、無線區域網路（MAN與LAN）OFDM編碼之發射接收機、VDSL接收機之類比前端電路、1000Base-T實體層接收發射機、10GBase-LX4實體層接收發射機、SONET OC-192系統之CDR電路設計與製作、DCATV, IS-95 CDMA, Pager System與IR之類比前端電路之設計製作、Bluetooth, GSM與無線區域網路之類比前端電路設計製作、Wireless LAN & SONET/Ethernet之limiting amplifier電路設計製作、DCATV QAM/VSB雙模式基頻處理器電路設計與製作、通訊與ADSL接收發射機之電路設計與製作、藍芽基頻接收機之電路設計與製作、PHS頻率合成器之電路設計與製作、無線區域網路RSSI之電路設計與製作。

Research Summary:

The main research areas include analog RF VLSI circuit design and mixed-mode VLSI circuit design. The research topics and achievements are Bio-medical system circuits, CMOS RF front-ends for 60-80GHz communication systems, CMOS LCD drivers, Cognitive Radio Communication Systems and Receiver frontends, wideband amplifier for UWB system, timing recovery circuit design and implementation for Impulse Radio system, VDSL transceiver (SCM/DMT) circuit design and implementation, wireless MAN OFDM transceivers circuit design and implementation, wireless LAN OFDM transceivers circuit design and implementation, analog front ends for VDSL receiver circuit design and implementation, 1000Base-T physical-layer transceivers circuit design and implementation, 10GBase-LX4 physical -layer transceivers circuit design and implementation, CDR for SONET OC-192 system, analog front ends for DCATV, IS-95 CDMA, Pager System & IR, RF front ends for Bluetooth, GSM & Wireless LAN, limiting amplifier for wireless LAN & SONET/Ethernet, DCATV QAM/VSB dual mode baseband processor circuit design and implementation, Communication & ADSL transceivers circuit design and implementation, Bluetooth baseband receiver circuit design and implementation, PHS frequency synthesizer and Wireless LAN RSSI circuit design and implementation.

 
Photo of Chorng-Kuang Wang

代表性著作 Selected Publication

  1. Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, and Chorng-Kuang Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2009
  2. Chao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu, and Chorng-Kuang Wang, “A 60-GHz Phased Array Receiver Front-End in 0.13-um CMOS Technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, no.10, 2341-2352, Oct. 2009
  3. Chao-Shiun Wang, Kun-Da Chu, and Chorng-Kuang Wang, “A 0.13µm CMOS 2.5Gb/s FSK demodulator using injection-locked technique,” IEEE Radio Frequency Integrated Circuits Symposium, Jun. 2009
  4. Chih-Feng Wu, Muh-Tian Shiue, and Chorng-Kuang Wang, “Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems -- Closed-Loop Derivation,” 2009 IEEE 69th Vehicular Technology Conference (VTC 2009-Spring), Apr. 2009
  5. Chien-chih Lin and Chorng-Kuang Wang, “Subharmonic Direct Frequency Synthesizer for Mode-1 MB-OFDM UWB System,” Symposium on VLSI Circuits, 2005. Digest of Technical Papers, Page(s):38 - 41, Jun. 2005
  6. Chien-chih Lin and Chorng-Kuang Wang, “A Semi-Dynamic Regenerative Frequency Divider for Mode-1 MB-OFDM UWB Hopping Carrier Generation,” IEEE ISSCC,2005, San Franscisco, 2005
  7. Tsung-Te Liu and Chorng-Kuang Wang, “A 0.8-8 GHz 9.7 mW Analog-Digital Dual-Loop Adaptive-Bandwidth DLL Based Multi-Phase Clock Generator,” European Solid-State Circuits Conference, pp375 – 378, 2004
  8. Chien-Chih Lin, Kuang-Hu Huang, Chorng-Kuang Wang, “A 15mW 280MHz 80dB Gain CMOS Limiting/Logarithmic Amplifier With Active Cascode Gain-Enhancement,” 28th European Solid-State Circuits Conference, Italy, Sept. 2002
  9. Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V CMOS 455KHz FM/FSK Demodulator using Feedforward Offset Cancellation Limiting Amplifier,” IEEE Journal of Solid-state Circuits, Vol. 36, No. 1, Jan. 2001
  10. Po-Chiun Huang, Yi-Huei Chen, and Chorng-Kuang Wang, “A 2-V 10.7MHz CMOS Limiting Amplifier/RSSI,” IEEE Journal of Solid-state Circuits, Vol.35, No.10, Sept. 2000