黃鐘揚的個人資料 - Profile of Chung-Yang Huang

黃鐘揚 Chung-Yang Huang

國立台灣大學電機工程學系
Professor, Department of Electrical Engineering, National Taiwan University
Associate Professor, Graduate Institute of Electronics Engineering, National Taiwan University

主要研究領域:

Major Research Areas:

(1) design verification for SoCs, (2) design for verifiability, (3) design automation and optimization, and (4) constraint satisfaction problems in electronic design automation (EDA) area.

研究領域摘要:

Research Summary:

Lab of Dependable Systems (3) Design Verification Team

The research focus of our lab is in the SoC (System on a Chip) design verification area, which includes:

  1. Sequential verification engines (e.g. ATPG, SAT, BDD, Arithmetic solver, etc)
  2. Network, communication, and multimedia IP verification techniques
  3. Design for Verifiability (DfV)
  4. System design analysis and debugging techniques
  5. Various applications of Constraint Satisfaction Problem (CSP)

We are implementing the above research topics into our own tools:

  1. Property Verification Framework
  2. IP Qualification Framework
Photo of Chung-Yang Huang