T.-W. Tong, T.-J. Chen, Y.-Y. Hsieh, and C.-H. Yang, “A 73.8K inference/mJ SVM Learning Accelerator for Brain Pattern Recognition,” IEEE J. Solid-State Circuits (JSSC) A-SSCC Special Issue, vol. 59, no. 10, 3357-3365, Oct. 2024
Y.-C. Lin, R.-H. Chiou, and C.-H. Yang, “A High-Throughput Constructive Interference Precoder for 16×16 MU-MIMO Systems,” IEEE Trans. Very Large Scale Integration (TVLSI), vol. 32, no. 10, 1878-1888, Jul. 2024
P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, “A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring,” IEEE J. Solid-State Circuits (JSSC), vol. 59, no. 6, 1899-1911, Jun. 2024
J.-F. Wu, Y.-C. Lin, C.-H. Yang, P.-H. Tseng, I.-J. Tsai, W.-H. Lin, W.-M. Hsu, “Clinical Utility of Anal Sphincter Relaxation Integral in Water-perfused and Solid-state High-resolution Anorectal Manometry,” Journal of the Formosan Medical Association, 123(2), 267-272, Feb. 2024
C.-H. Yang, Y.-C. Wu, Y.-L. Chen, C.-H. Lee, J.-H. Hung, and C.-H. Yang, “An FM-index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-end Short-read Mapping,” IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 17, no. 6, 1331-1341, Dec. 2023
S.-J. Yu, Y.-C. Lee, L.-H. Lin, and C.-H. Yang, “An Energy-efficient Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices,” IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 6, 1810-1819, Jun. 2023
H.-Y. Shen, Y.-C. Lee, Z.-W. Tong, and C.-H. Yang, “A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator,” IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 2, 520-529, Feb. 2023
Y.-Y. Hsieh, Y.-C. Lin, and C.-H. Yang, “A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction,” IEEE J. Solid-State Circuits (JSSC), vol. 58, no. 1, 167-176, Jan. 2023
Y.-S. Lin, Y.-P. Wu, Y.-C. Wu, P.-L. Lee, and C.-H. Yang, “Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal,” IEEE Journal of Biomedical and Health Informatics (JBHI), vol. 26, no. 11, 5473-5481, Nov. 2022
C.-C. Kao, C.-E. Chen, C.-H. Yang, “Hybrid Precoding Baseband Processor for 64x64 Millimeter Wave MIMO Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 69, no. 4, 1765-1773, Apr. 2022
S.-H. Wang, Y.-K. Huang, C.-Y. Chen, L.-Y. Tang, Y.-F. Tu, P.-C. Chang, C.-F. Lee, C.-H. Yang, C.-C. Hung, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, “Design of a Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Evoked Compound Action Potential Acquisition and Its In Vivo Verification,” IEEE J. Solid-State Circuits (JSSC) A-SSCC 2020 Special Issue, vol. 56, no. 10, 3062-3076, Oct. 2021
J.-F. Wu, W.-C. Hsu, I.-J. Tsai, T.-W. Tong, Y.-C. Lin, C.-H. Yang, and P.-H. Tseng, “Bolus transit of upper esophageal sphincter on high-resolution impedance manometry study correlate with the laryngopharyngeal reflux symptoms,” Scientific Reports, 11(1), 1-9, Oct. 2021
Y.-L. Chen, B.-Y. Chang, C.-H. Yang, and T.-D. Chiueh, “A High-throughput FPGA Accelerator for Short-read Mapping of the Whole Human Genome,” IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 32, no. 6, 1465-1478, Jun. 2021
C.-Y. Yeh, T.-C. Chu, C.-E. Chen, C.-H. Yang, “A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 65, no. 11, pp. 3918-3928, Nov. 2018
J.-F. Wu, C. Chung, P.-H. Tseng, I.-J. Tsai, Y.-H. Lin, C.-H. Yang, “Distal contractile to impedance integral ratio assist the diagnosis of pediatric ineffective esophageal motility disorder,” Pediatric Research, vol. 84, no. 6, 849-853, Oct. 2018
T.-I Chou, K.-H. Chang, J.-Y. Jhang, S.-W. Chiu, G. Wang, C.-H. Yang, H. Chiueh, H. Chen, C.-C. Hsieh, M.-F. Chang, K.-T. Tang, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip,” IEEE Trans. Circuits & Systems II (TCAS-II), vol. 65, no. 10, pp. 365-1369, Jul. 2018
J.-F. Wu, C.-H. Lu, C.-H. Yang, I-J. Tsai, “Diagnostic Role of Anal Sphincter Relaxation Integral (ASRI) in High-resolution Anorectal Manometry for Hirschsprung's Disease in Infants,” Journal of Pediatrics, vol. 194, pp. 136-141, Mar. 2018
Y.-C. Tsai, C.-E. Chen, C.-H. Yang, “A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 64, no. 2, pp. 446-456, Feb. 2017
M.-R. Li, C.-H. Yang, Y.-L. Ueng, “A 5.28-Gbps LDPC Decoder with Time-domain Signal Processing for IEEE 802.15.3c Applications,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 2, pp. 592-604, Feb. 2017
C.-H. Chang, M.-T. Chou, Y.-C. Wu, T.-W. Hong, Y.-L. Li, C.-H. Yang, and J.-H. Hung, “sBWT: Memory Efficient Implementation of the Hardware-acceleration-friendly Schindler Transform for the Fast Biological Sequence Mapping,” Bioinformatics, 32.22, pp. 3498-3500, Jul. 2016
C.-Y. Lee, P.-H. Hsieh, and C.-H. Yang, “A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic with 70% Energy Saving,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 63, no. 1, pp. 70-79, Jan. 2016
W.-H. Wu, W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 62, no. 10, pp. 2512-2522, Oct. 2015
C.-H. Yang, C.-W. Chou, C.-S. Hsu, C.-E. Chen, “A Systolic Array Based GTD Processor with a Parallel Algorithm,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 62, no. 4, pp. 1099-1108, Apr. 2015
C.-H. Yang, Y.-H. Shih, and H. Chiueh, “An 81.6μW FastICA Processor for Epileptic Seizure Detection,” IEEE Trans. Biomedical Circuits & Systems (TBioCAS), vol. 9, no.1, pp. 60-71, Feb. 2015
C.-E. Chen, Y.-C. Tsai, and C.-H. Yang, “An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems,” IEEE Trans. Wireless Communications (TWC), vol. 14, no. 1, pp. 343-352, Jan. 2015
C.-H. Yang, T.-Y. Huang, M.-R. Li, and Y.-L. Ueng, “A 5.4μW Soft-Decision BCH Decoder for Wireless Body Area Networks,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 61, no. 9, pp. 2721-2729, Sept. 2014
C.-C. Cheng, J.-D. Yang, C.-H. Yang, and Y.-L. Ueng, “A Fully-Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 61, no. 9, pp. 2738-2746, Sept. 2014
S.-F. Liang, Y.-C. Chen, Y.-L. Wang, P.-T. Chen, C.-H. Yang, and H. Chiueh, “A Hierarchical Approach for On-line Temporal Lobe Seizure Detection in Long-term Intracranial EEG Recordings,” J. Neural Engineering (JNE), vol. 10, no. 4, pp. 1-14, May 2013
T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, “A 7.4mW 200MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios,” IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 9, pp. 2235-2245, Sept. 2012
C.-H. Yang, T.-H. Yu, and D. Marković, “Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example,” IEEE J. Solid-State Circuits (JSSC), vol. 47, no. 3, pp. 757-767, Mar. 2012
C.-H. Yang and D. Marković, “A Flexible DSP Architecture for MIMO Sphere Decoding,” IEEE Trans. Circuits & Systems I (TCAS-I), vol. 56, no. 10, pp. 2301-2314, Oct. 2009
Conference & proceeding papers:
C.-W. Chang, I.-T. Lin, C.-H. Yang, “A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices,” Int. Symposium on VLSI Circuits (VLSI Circuits), Jun. 2024
P.-S. Wu, Y.-C. Lin, C.-H. Yang, “A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-based Speculation,” Int. Symposium on VLSI Circuits (VLSI Circuits), Jun. 2024
Y.-C. Lin, R.-H. Chiou, Y.-C. Lin, and C.-H. Yang, “A 919GMACs/J Reconfigurable SIMD Array Processor for Baseband Signal Processing,” Int. VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Apr. 2024
Y.-C. Lin, C. Park, W. Zhao, N. Sun, Y. Chae, and C.-H. Yang, “A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing,” Int. Symposium on VLSI Circuits (VLSI Circuits), Jun. 2023
Y.-L. Lo, Y.-C. Lo and C.-H. Yang, “A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices,” Int. Symposium on VLSI Circuits (VLSI Circuits), Jun. 2023
Y.-H. Tsai, Y.-C. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, S.-H. Chen, C.-S. Chen, C.-H. Yang, “A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022
C.-C. Kao, Y.-Y Hsieh, C.-H. Chen, and C.-H. Yang, “Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression,” Int. Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2022
W.-C. Huang, I.-T. Lin, W.-C. Chen, L.-Y. Lin, N.-S. Chang, C.-P. Lin, C.-S. Chen, C.-H. Yang, “A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality,” Int. Symposium on VLSI Circuits (VLSI Circuits), 42-43, Jun. 2022
Z.-S. Fu, Y.-C. Lee, A. Park, C.-H. Yang, “A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training,” Int. Symposium on VLSI Circuits (VLSI Circuits), 40-41, Jun. 2022
Y.-Y. Hsieh, Y.-C. Lin, C.-H. Yan, “A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction,” Int. Solid-State Circuits Conference (ISSCC), 506-508, Feb. 2022
P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, “A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021
S.-J. Yu, Y.-C. Lee, and C.-H Yang, “A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021
Y.-L. Lo and C.-H. Yang, “A Color Doppler Processing Engine with An Adaptive Clutter Filter for Portable Ultrasound Imaging Devices,” Proc. Int. Conf. Acoustics, Speech and Signal Processing (ICASSP), Jun. 2021
S.-A. Huang, Y.-Y. Hsieh, and C.-H. Yang, “Design Optimization for ADMM-Based SVM Training Processor for Edge Computing,” Proc. Int. Conference on Artificial Intelligence Circuits and Systems (AICAS), Jun. 2021
H.-Y. Shen, Y.-C. Lee, T.-W. Tong, and C.-H. Yang, “A 91mW 90fps Super-Resolution Processor for Full HD Images,” Int. Solid-State Circuits Conference (ISSCC), 66-67, Feb. 2021
Y.-P. Wang, C.-C. Wen, C.-C. Kao, C.-J. Huang, D.-Z. Liu, and C.-H. Yang, “Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax,” Global Communications Conference (GLOBECOM), Dec. 2020
S.-H. Wang, Y.-K. Huang, C.-Y. Chen, C.-F. Lee, C.-H. Yang, C.-C. Hung, C.-H. Liu, M.-D. Ker, and C.-Y. Wu, “Improved Design and in Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2020
Y.-Y. Hsieh, Y.-C. Lee, C.-H. Yang, “A CycleGAN Accelerator for Unsupervised Learning on Mobile Devices,” Int. Symposium Circuits and Systems (ISCAS), Oct. 2020
H. Chiueh, C.-H. Yang, C. H.-P. Wen, C.-G. Yang, P.-H. Chien, C.-Y. Hung, Y.-J. Chen, Y.-P. Wang, C.-F. Chiu, J. Lin, “Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS,” Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), Aug. 2020
C. Chung and C.-H. Yang, “A 1.5μJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots,” Int. Solid-State Circuits Conference (ISSCC), 324-325, Feb. 2020
C.-H. Lu, Y.-C. Wu, and C.-H. Yang, “A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training,” IEEE Asian Solid-State Circuits Conference (A-SSCC), 65-58, Nov. 2019
W.-C. Sun, Y.-C. Su, Y.-L. Ueng, and C.-H. Yang, “An LDPC-Coded SCMA Receiver with Multi-User Iterative Detection and Decoding,” IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sept. 2019
Y.-C. Lee, T.-S. Chi, and C.-H. Yang, “A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices,” Proc. Int. Conference on Artificial Intelligence Circuits and Systems (AICAS), Mar. 2019
W.-C. Huang and C.-H. Yang, “RISC-V Architecture Optimization through Extensible Instruction Sets and Custom Accelerators,” RISC-V Workshop, Mar. 2019
Y.-Z. Wang, J. Wu, S.-H. Chen, Mango C.-T. Chao, and C.-H. Yang, “Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs,” Proc. Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), Mar. 2019
T.-I Chou, K.-H. Chang, J.-Y. Jhang, S.-W. Chiu, G. Wang, C.-H. Yang, H. Chiueh, H. Chen, C.-C. Hsieh, M.-F. Chang, K.-T. Tang, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip,” IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sept. 2018
C.-Y. Yeh, T.-C. Chu, C.-E. Chen, C.-H. Yang, “A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems,” IEEE Int. Symposium on Integrated Circuits and Systems (ISICAS), Sept. 2018
Y.-Z. Wang, Y.-P. Wang, Y.-C. Wu, C.-H. Yang, “A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals,” Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 261-262, Jun. 2018
S.-A. Huang, K.-C. Chang, H.-H. Liou, and C.-H. Yang, “A 1.9mW SVM Processor with On-chip Active Learning for Epileptic Seizure Control,” Int. Symposium on VLSI Circuits (VLSI Circuits), pp. 259-260, Jun. 2018
C.-H. Chiang, S.-A. Huang, C.-E. Chen, and C.-H. Yang, “A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems,” Int. Symposium Circuits and Systems (ISCAS), pp. 1-5, May 2018
W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors,” IEEE Vehicular Technology Conf. (VTC-Spring), Jun. 2017
Y.-T. Chen, C.-C. Cheng, T.-L. Tsai, W.-C. Sun, Y.-L. Ueng, C.-H. Yang, “A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 330-331, Jun. 2017
H.-T. Lin, Y.-C. Wu, P.-H. Hsieh, C.-H. Yang, “Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables,” Int. Symposium Circuits and Systems (ISCAS), May 2017
Y.-C. Wu, J.-H. Hung, C.-H. Yang, “A 135mW Fully Integrated Data Processor for Next-Generation Sequencing,” Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2017
T.-I. Chou, S.-W. Chiu, K.-H. Chang, Y.-J. Chen, C.-T. Tang, C.-H. Shih, C.-C. Hsieh, M.-F. Chang, C.-H. Yang, H. Chiueh, and K.-T. Tang, “Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease,” IEEE Biomedical Circuits & Systems Conf. (BioCAS), pp. 592-595, Nov. 2016
H.-M. Liu, Y.-J. Lin, Y.-C. Lee, C.-Y. Lee, C.-H. Yang, “A 98.6μW Acoustic Signal Processor for Fully-Implantable Cochlear Implants,” Int. Symposium VLSI Design, Automation & Test (VLSI-DAT), pp. 1-4, Apr. 2016
W.-C. Liu, C.-D. Chan, S.-A. Huang, C.-W. Lo, C.-H. Yang, S.-J. Jou, “Error-Resilient Sequential Cells with Successive Time Borrowing for Stochastic Computing,” Proc. Int. Conf. Acoustics, Speech and Signal Processing (ICASSP), pp. 6545-6549, Mar. 2016
J.-H. Hung, P.-Y. Wang, B.-Y. Tsui, C.-H. Yang, “A Concept of Heterogeneous Circuits with Epitaxial Tunnel Layer Tunnel FETs,” Proc. Int. Conf. Solid State Devices and Materials (SSDM), Sept. 2015
W.-H. Wu, W.-C. Sun, C.-H. Yang, and Y.-L. Ueng, “A 794Mbps 135mW Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 102-103, Jun. 2015
T.-J. Chen, S.-C. Lee, C.-H. Yang, C.-F. Chiu, and H. Chiueh, “A 28.6μW Mixed-Signal Processor for Epileptic Seizure Detection,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 52-53, Jun. 2013
T.-H. Yu, C.-H. Yang, and D. Marković, “An Energy-Efficient VLSI Architecture for Wideband Spectrum Sensing for Cognitive Radios,” Proc. Global Communications Conference (GLOBECOM), pp. 1-6, Dec. 2011
F.-L. Yuan, C.-H. Yang, and D. Marković, “A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection,” Proc. Global Communications Conference (GLOBECOM), pp. 1-6, Dec. 2011
V. Karkare, S. Gibson, C.-H. Yang, H. Chen, and D. Marković, “A 75μW, 16-Channel Neural Spike-Sorting Processor with Unsupervised Clustering,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 252-253, Jun. 2011
T.-H. Yu, C.-H. Yang, D. Čabrić, and D. Marković, “A 7.4mW 200MS/s Spectrum Sensing Digital Baseband Processor for Cognitive Radios,” Proc. Int. Symposium on VLSI Circuits (VLSI),, pp. 254-25, Jun. 2011
C.-H. Yang, T.-H. Yu, and D. Marković, “A 5.8mW 3GPP-LTE Compliant 8x8 MIMO Sphere Decoder Chip with Soft-Outputs,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 209-210, Jun. 2010
C.-H. Yang and D. Marković, “A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications,” Proc. Global Communications Conference (GLOBECOM), pp. 3297-3301, Dec. 2008
R. Nanda, C.-H. Yang, D. Marković, “DSP Architecture Optimization in Matlab/Simulink Environment,” Proc. Int. Symposium on VLSI Circuits (VLSI), pp. 192-193, Jun. 2008
C.-H. Yang and D. Marković, “A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels,” Proc. Int. Conference on Communications (ICC), pp. 725-731, May 2008
Y.-L. Ueng, W.-C. Sun, W.-H. Wu, C.-H. Yang, “SISO (Soft Input Soft Output) System for Use in a Wireless Communication System and Operational Method Thereof,” US 9,973,217, May 2018
C.-H. Yang and Y.-C. Tsai, “Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof,” US 9,306,641, Apr. 2016
S.-J. Jou, C.-H. Yang, W.-C. Liu, C.-W. Lo, C.-D. Chan, “Sampling Circuit and Master-Slave Flip-Flop,” US 9,608,603 B2, Mar. 2016
C.-H. Yang and Y.-C. Tsai, “Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof,” US 9,231,679, Jan. 2016
C.-H. Yang, C.-E. Chen, and C.-W. Jou, “Method and system for constrained power allocation in the multi-input multi-output systems,” US 9,231,674, Jan. 2016
Y.-L. Ueng, C.-H. Yang, M. R. Li, “Unequal Bit-reliability Information Storage Method for Communication and Storage Systems,” US 9,058,880 B2, Jun. 2015