吳安宇特聘教授的著作列表 - Publication List of An-Yeu (Andy) Wu

Publication List of 吳安宇 An-Yeu (Andy) Wu

Journal articles & book chapters:

  1. 82. Ching-Chun Liao, Ting-Sheng Chen, and An-Yeu Wu, “Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit,” IEEE Trans. Circuits and Systems I: Regular Papers (TCAS-I), 66, 2987~3000, Aug. 2019
  2. Ding-Yuan Lee, Ching-Che Wang, and An-Yeu Wu, “Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor,” IEEE Trans. Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 27, no. 6, 1450~1454, Jun. 2019
  3. Hung-Yi Cheng, Ching-Chun Liao, and An-Yeu (Andy) Wu, “Joint Multi-Beam Training and Codebook Design for Indoor High-throughput Transmissions under Limited Training Steps,” IEEE Transactions on Vehicular Technology (TVT), vol. 68, no. 6, 5585~5597, Mar. 2019
  4. Ting-Sheng Chen, Hung-Chi Kuo, and An-Yeu Wu, “A 232-to-1996KS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, No. 1, pp. 307-317, Jan. 2019
  5. Cheng-Rung Tsai and An-Yeu Wu, “Structured Random Compressed Channel Sensing for Millimeter-Wave Large-Scale Antenna Systems,” IEEE Trans. Signal Processing (TSP), vol. 66 No.19, 5096~5110, Oct. 2018
  6. Ching-Yao Chou, En-Jui Chang, Huai-Ting Li, An-Yeu Wu, “Low-Complexity Privacy-Preserving Compressive Analysis Using Subspace-Based Dictionary for ECG Telemonitoring System,” IIEEE Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 12, no. 4, pp. 801~811, Aug. 2018
  7. Chih-Hao Chen, Sung-Chun Tang, Ding-Yuan Lee, Jiann-Shing Shieh, Dar-Ming Lai, An-Yeu Wu & Jiann-Shing Jeng, “Impact of Supratentorial Cerebral Hemorrhage on the Complexity of Heart Rate Variability in Acute Stroke,” Scientific reports, Jul. 2018
  8. Cheng-Rung Tsai, Yu-Hsin Liu, and An-Yeu Wu, “Efficient Compressive Channel Estimation for Millimeter-Wave Large-Scale Antenna Systems,” IEEE Trans. Signal Processing (TSP), vol. 66, No. 9, pp. 2414-2428, May 2018
  9. Sheng-Chun Kao, Ding-Yuan Lee, Ting-Sheng Chen, and An-Yeu Wu, “Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing,” IEEE/ACM Transactions on Networking, vol. 26, no. 2, pp. 1004-1017, Apr. 2018
  10. Huai-Ting Li, Ching-Yao Chou, Yuan-Ting Hsieh, Wei-Ching Chu, and An-Yeu (Andy) Wu, “Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy,” IEEE Trans. Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 25, pp. 2803-2816, Oct. 2017
  11. Sung-Chun Tang, Pei-Wen Huang, Chi-Sheng Hung, Shih-Ming Shan, Yen-Hung Lin, Jiann-Shing Shieh, Dar-Ming Lai, An-Yeu Wu, and Jiann-Shing Jeng, “Identification of Atrial Fibrillation by Quantitative Analyses of Fingertip Photoplethysmogram,” Scientific Reports 7, Nature, Apr. 2017
  12. Chiang-Hen Chen, Cheng-Rung Tsai, Yu-Hsin Liu, Wei-Lun Hung, and An-Yeu (Andy) Wu, “Compressive Sensing (CS) Assisted Low-Complexity Beamspace Hybrid Precoding for Millimeter-Wave MIMO Systems,” IEEE Trans. Signal Processing (TSP), vol. 65, pp. 1412-1424, Mar. 2017
  13. Yu-Yin Chen, En-Jui Chang, Hsien-Kai Hsin, Kun-Chih Chen, and An-Yeu (Andy) Wu, “Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems,” IEEE Trans. Parallel and Distributed Systems (TPDS), vol.28, pp. 838-849, Mar. 2017
  14. Yu-Min Lin, Yi Chen, Nai-Shan Huang, and An-Yeu (Andy) Wu, “Low-Complexity Stochastic Gradient Pursuit (SGP) Algorithm and Architecture for Robust Compressive Sensing Reconstruction,” IEEE Trans. Signal Processing, vol. 65, pp. 638-650, Feb. 2017
  15. Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu and An-Yeu (Andy) Wu, “Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing,” IEEE Trans. Circuits and Systems-I: Regular Papers (TCAS-I), vol. 63, pp. 1661-1672, Oct. 2016
  16. Yu-Min Lin, Jie-Fang Zhang, Jing Geng, and An-Yeu (Andy) Wu, “Structural Scrambling of Circulant Matrices for Cost-effective Compressive Sensing,” Journal of Signal Processing Systems, Oct. 2016
  17. Hung-Yi Cheng, and An-Yeu (Andy) Wu, “Unified Low-complexity Decision Feedback Equalizer with Adjustable Double Radius Constraint,” Digital Signal Processing(DSP), vol.51, 82~91, Apr. 2016
  18. Kun-Chih (Jimmy) Chen, Chih-Hao Chao, An-Yeu (Andy) Wu, “Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managementse,” IEEE Circuits and Systems Magazine, vol. 15, issue 4, 45~69, Nov. 2015
  19. Hsien-Kai Hsin, En-Jui Chang, Kuan-Yu Su, and An-Yeu (Andy) Wu, “Ant Colony Optimization-based Adaptive Network-on-Chip Routing Framework Using Network Information Region,” IEEE Trans. Computers(TC), vol. 64, issue. 8, pp. 2119-2131, Aug. 2015
  20. Yu-Min Lin, Huai-Ting Li, Ming-Han Chung, and An-Yeu (Andy) Wu, “Byte-Reconfigurable LDPC Codec Design with Application to High-Performance ECC of NAND Flash Memory Systems,” IEEE Trans. Circuits and Systems-I: Regular Papers (TCAS-I), vol. 62, No. 7, pp. 1794-1804, Jul. 2015
  21. En-Jui Chang, Hsien-Kai Hsin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Regional ACO-Based Cascaded Adaptive Routing for Load Balancing in Mesh-Based Network-on-Chip Systems,” IEEE Trans. Computers(TC), vol. 64, issue 3, pp. 868-875, Mar. 2015
  22. Kun-Chih Chen, En-Jui Chang, Huai-Ting Li, and An-Yeu (Andy) Wu, “RC-based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-based 3D NoCs,” IEEE Trans. Parallel and Distributed Systems(TDPS), vol. 26, issue 1, pp. 206-218, Jan. 2015
  23. Sung-Chun Tang, Hsiao-I Jen, Yen-Hung Lin, Chi-Sheng Hung, Wei-Jung Jou, Pei-Wen Huang, Jiann-Shing Shieh, i-Lwun Ho, Dar-Ming Lai, An-Yeu Wu, Jiann-Shing Jeng, Ming-Fong Chen, “Complexity of heart rate variability predicts outcome in intensive care unit admitted patients with acute stroke,” Journal of Neurology, Neurosurgery and Psychiatry (JNNP), vol. 86, issue 1, pp.95-100, Jan. 2015
  24. Hsien-Kai Hsin, En-Jui Chang, Chia-An Lin, and An-Yeu (Andy) Wu, “Ant Colony Optimization-Based Fault-Aware Routing in Mesh-based Network-on-Chip Systems,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, issue 11, pp. 1693-1705, Nov. 2014
  25. Hsien-Kai Hsin, En-Jui Chang, and An-Yeu (Andy) Wu, “Spatial-Temporal Enhancement of ACO-based Selection Schemes for Adaptive Routing in Network-on-Chip Systems,” IEEE Trans. Parallel and Distributed Systems (TPDS), vol. 25, issue 6, pp. 1626-1367, Jun. 2014
  26. Yu-Hao Chen, Yu-Min Lin, Kuan-Yu Ho, An-Yeu Wu, and Pai-Chi Li, “Low-Complexity Motion-Compensated Beamforming Algorithm and Architecture for Synthetic Transmit Aperture in Ultrasound Imaging,” IEEE Trans. Signal Processing (TSP), vol. 62, no.4, pp. 840-851, Feb. 2014
  27. En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.33, issue 1, pp.113-126, Jan. 2014
  28. Wen-Chung Shen, Yu-Hao Chen, and An-Yeu (Andy) Wu, “Low-Complexity Sinusoidal-Assisted EMD (SAEMD) Algorithms for Solving Mode-Mixing Problems in HHT,” Digital Signal Processing(DSP), vol.24, pp170-186, Jan. 2014
  29. Chih-Hao Chao, Kun-Chih Chen, and An-Yeu (Andy) Wu, “Routing-Based Traffic Migration and Buffer Allocation Schemes for Three-Dimensional Network-on-Chip Systems with Thermal Limit,” IEEE Trans. Very Large Scale Integration Systems (TVLSI), vol.21, no.11, pp. 2118-2131, Nov. 2013
  30. Cheng-Hung Lin, Chun-Yu Chen, En-Jui Chang, and An-Yeu (Andy) Wu, “Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems,” Journal of Signal Processing Systems (JSPS), vol.73, Issue 2, pp. 109-122, Nov. 2013
  31. Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, and An-Yeu (Andy) Wu, “Topology-Aware Adaptive Routing for Non-Stationary Irregular Mesh in Throttled 3D NoC Systems,” IEEE Trans. Parallel and Distributed Systems (TPDS), vol.24, no.10, pp. 2109-2120, Oct. 2013
  32. Hsien-Kai Hsin, En-Jui Chang and An-Yeu Wu, “Implementation of ACO-based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems,” IEEE Embedded Systems Letters (ESL), vol. 5, No. 3, pp.46-49, Sept. 2013
  33. Chih-Hao Chao, Kun-Chih Chen, Tsu-Chu Yin, Shu-Yen Lin and An-Yeu (Andy) Wu, “Transport Layer Assisted Routing for Run-Time Thermal Management of 3D NoC Systems,” ACM Trans. Embedded Computing Systems (TECS), vol.13, no.1, article 11, Aug. 2013
  34. Wen-Chung Shen, Hsiao-I Jen, and An-Yeu (Andy) Wu, “New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform,” IEEE Trans. Circuits and Systems, Part-II: Express Briefs (TCAS-II), vol. 60, no. 8, pp. 532-536, Aug. 2013
  35. Yi-Hsuan Lin, Yu-Hao Chen, Chun-Yuan Chu, Cheng-Zhou Zhan and An-Yeu Wu, “Dual-Mode Low-Complexity Codebook Searching Algorithm and VLSI Architecture for LTE/LTE-Advanced Systems,” IEEE Trans. Signal Processing (TSP), vol. 61, no.14, pp. 3545-3562, Jul. 2013
  36. Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, and An-Yeu (Andy) Wu, “Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems,” IEEE Trans. Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 21, no.4, pp.747-760, Apr. 2013
  37. Jie-Ren Shih, Yongbo Hu, Ming-Chun Hsiao, Ming-Shing Chen, Wen-Chung Shen, Bo-Yin Yang, An-Yeu Wu, and Chen-Mou Cheng, “Securing M2M with Post-Quantum Public-Key Cryptography,” IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 3, no. 1, pp.106-116, Mar. 2013
  38. Yu-Hao Chen, Zih-Ling Liu, I-Hsuan Lee, and An-Yeu (Andy) Wu, “Motion Artifact Elimination Algorithm and Architecture for Eigen-based Clutter Filter in Color Doppler Processing,” International Journal of Electrical Engineering(IJEE), vol. 19, no. 6, pp. 245-254, Dec. 2012
  39. Chun-Yuan Chu and An-Yeu Wu, “Power-Efficient State Exchange Scheme for Low Latency SMU Design of Viterbi Decoder,” Journal of Signal Processing Systems (JSPS), vol. 68, No. 2, pp. 233-245, Aug. 2012
  40. Min-An Chao, Xin-Yu Shih and An-Yeu Wu, “Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders,” Journal of Signal Processing Systems (JSPS), vol. 68, No. 2, pp. 183-202, Aug. 2012
  41. Cheng-Zhou Zhan, Yen-Liang Chen and An-Yeu Wu, “Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems,” IEEE Trans. Signal Processing(TSP), vol. 60, pp. 3264-3277, Jun. 2012
  42. Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, and An-Yeu Wu, “Multi-prediction particle filter for efficient parallelized implementation,” on-line publication in EURASIP Journal on Advances in Signal Processing, Vol. 2011, Number 1/53, Sept. 2011
  43. Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, and An-Yeu Wu, “A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks,” Design Automation for Embedded Systems, vol.15, no.2, pp. 111-132, Apr. 2011
  44. Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq-Kuen Lee, Yuan-Hua Chu, and An-Yeu Wu, “Parallel Architecture Core (PAC) - the First Multi-core Application Processor SoC in Taiwan Part I: Hardware architecture & Software Development Tools,” Journal of Signal Processing Systems, vol.62, no.3, pp. 373-382, Mar. 2011
  45. Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei-Kuan Shih, and An-Yeu Wu, “Parallel Architecture Core (PAC) - the First Multi-core Application Processor SoC in Taiwan Part II: Application Programming,” Journal of Signal Processing Systems, vol.62, no.3, pp. 383-402, Mar. 2011
  46. Chen-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, “Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 2, pp. 305-318, Feb. 2011
  47. Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm,” IEEE Trans. Circuits and Systems, Part-II: Express Briefs (SCI, EI), vol. 57, no. 6, vol. 57, no. 6, Jun. 2010
  48. Yen-Liang Chen and An-Yeu Wu, “Generalized Pipelined Tomlinson–Harashima Precoder Design Methodology With Build-In Arbitrary Speed-Up Factors,” IEEE Trans. Signal Processing, vol. 58, no.4, pp. 2375-2382, Apr. 2010
  49. I-Chyn Wey, You-Gang Chen, Chang-Hong Yu, An-Yeu Wu, and Jie Chen, “Design and Implementation of Cost-Efficient Probabilistic-Based Noise-Tolerant VLSI Circuits,” IEEE Trans.Circuits and Systems Part-I: Regular Papers, vol. 56, no. 11, pp. 2411-2424, Nov. 2009
  50. Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu Wu, “Multilevel LINC system designs for power efficiency enhancement of transmitters,” IEEE Journal of Selected Topics in Signal Processing, vol.3, no. 3, pp. 523-532, Jun. 2009
  51. Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, and An-Yeu Wu, “Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System,” International Journal of Electrical Engineering, vol. 16, no. 3, pp. 203-212, Jun. 2009
  52. Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, and An-Yeu Wu, “Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor,” International Journal of Electrical Engineering, vol. 16, no. 3, pp. 213-222, Jun. 2009
  53. Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu, and Tsung-Han Tsai, “Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder,” IEEE Trans. Circuits and Systems Part I: Regular Paper, vol. 56, no. 5, pp. 1005-1016, May 2009
  54. I-Chyn Wey, You-Gang Chen, and An-Yeu Wu, “Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits,” IEEE Trans. Very Large Scale Integration (VLSI) Systems (Brief), vol. 16, no.12, pp. 1708-1712, Dec. 2008
  55. Fan-Min Li, Cheng-Hung Lin, and An-Yeu Wu, “Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel,” Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 10, pp. 1358-1371, Oct. 2008
  56. Shu-Yen Lin, Chun-Hsiang Huang, Chih-hao Chao, Keng-Hsien Huang, and An-Yeu Wu, “Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks,” IEEE Trans. Computers, vol. 52, pp. 1156–1168, Sept. 2008
  57. Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, and An-Yeu Wu, “Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme,” Journal of Signal Processing Systems, vol. 52, no. 1, pp. 59-73, Jul. 2008
  58. Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, “An 8.29mm2 52mW Multi-mode LDPC Decoder Design for Mobile WiMAX System in 0.13um CMOS Process,” IEEE Jour. Solid-State Circuits, vol. 43, no. 3, pp. 672-683, Mar. 2008
  59. Jyh-Ting Lai, An-Yeu Wu, and Chien-Hsiung Lee, “A Systematic Design Approach on the Band-Tracking Packet Detector (BT-PD) for OFDM-Based UWB Systems,” IEEE Trans. Vehicular Technology, vol. 56, no. 6, pp. 3791-3806, Nov. 2007
  60. Fan-Min Li, and An-Yeu Wu, “On The New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold,” IEEE Trans. Signal Processing, vol. 55, no. 11, pp. 5506-5516, Nov. 2007
  61. Jyh-Ting Lai, An-Yeu Wu, and Chien-Hsiung Lee, “Joint AGC-Equalization (Joint AGC-EQ) Algorithm and VLSI Architecture For Wirelined Transceiver Designs,” IEEE Trans. Very Large Scale Integration (VLSI) Systems (Brief), vol. 15, no.2, pp. 236-240, Feb. 2007
  62. Huai-Yi Hsu, An-Yeu Wu, and Jih-Chiang Yeo, “Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems,” IEEE Trans. Circuits and Systems, Part-II, vol. 53, no. 11, pp. 1245–1249, Nov. 2006
  63. Chih-Hsiu Lin, An-Yeu Wu, and Fan-Min Li, “High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems,” in IEEE Trans. Circuits and Systems, Part-II: Express Briefs, vol. 53, no. 9, pp. 911-915, Sept. 2006
  64. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, “Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Finite-Field Processing Element,” IEEE Trans. VLSI Systems, vol. 14, no. 5, pp. 489-500, May 2006
  65. Chih-Hsiu Lin and An-Yeu Wu, “Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) Algorithm and Architecture for Scaling-Free High-Performance Rotational Operations,” IEEE Trans. Circuits and Systems, vol. 52, no. 11, 2385-2396, Nov. 2005
  66. Chih-Hsiu Lin and A.-Y. Wu, “Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture,” IEEE Trans. Signal Processing, vol. 53, no. 8, 3325-3336, Aug. 2005
  67. 15. Hung-Yang Ko, Chung-chun Chen, Yi-Chen Wang and An-Yeu Wu, “用於無線通訊系統之極座標發射機 (Polar Transmitter for Wireless Communication System),” 國立臺灣大學「台大工程」學刊, no. 93, 39-49, Feb. 2005
  68. Meng-Da Yang, An-Yeu Wu, and Jyh-Ting (Justin) Lai, “High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, 218-226, Feb. 2004
  69. Meng-Da Yang, An-Yeu Wu, and Jyh-Ting Lai, “Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique,” IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 51, no. 2, 57-60, Feb. 2004
  70. Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, and An-Yeu Wu, “VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems,” Special Issue on “Signal Processing for Broadband Access Systems: Techniques and Implementations, EURASIP Journal on Applied Si, no. 13, pp. 1306-1316, Dec. 2003
  71. Cheng-Shing Wu, An-Yeu Wu, and Chih-Hsiu (Zhi-Xiu) Lin, “A High-performance/Low-latency Vector Rotational CORDIC Architecture Based on Extended Elementary Angle Set and Trellis-based Searching Schemes,” IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 50, no. 9, pp. 589-601, Sept. 2003
  72. Huai-Yi Hsu, Sheng-Feng Wang, and An-Yeu Wu, “A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm,” Special Issue on Signal Processing Systems: Part II, Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Tech, vol. 34, no. 3, pp. 251-259, Jul. 2003
  73. Hsin-Chung Wang, Chih-Hsiu Lin, and An-Yeu Wu, “具成本效益的AES加密引擎之設計與實現(Design and Implementation of a Cost-efficient AES Cryptographic Engine),” 國立臺灣大學「台大工程」學刊, no. 88, pp. 51-60, Jun. 2003
  74. Cheng-Shing Wu and An-Yeu Wu, “A Novel Echo Cancellation Algorithm and Architecture Based on Multi-Path Adaptive Interpolated FIR Filter,” Journal of the Chinese Institute of Electrical Engineering, Part E, vol.10, no.2, pp.135-143, May 2003
  75. Tsun-Shan Chan, Jen-Chih Kuo, and An-Yeu Wu, “A Reduced-complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems,” EURASIP Journal on Applied Signal Processing, vol. 2002, no. 9, pp. 961-974, Sept. 2002
  76. An-Yeu Wu and Cheng-Shing Wu, “A Unified View for Vector Rotational CORDIC Algorithms and Architectures based on Angle Quantization Approach,” IEEE Trans. Circuits and Systems Part-I: Fundamental Theory and Applications, vol. 49, no. 10, pp. 1442-1456, Sept. 2002
  77. Cheng-Shing Wu and An-Yeu Wu, “Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Architecture,” IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 48, no. 6, pp. 548-561, Jun. 2001
  78. An-Yeu Wu and K. J. R. Liu, “Algorithm-Based Low-Power Transform Coding Architectures: The Multirate Approach,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, pp. 707-718, Dec. 1998
  79. K. J. R. Liu, An-Yeu Wu, A. Raghupathy, and J. Chen, “Algorithm-Based Low-Power and High-Performance Multimedia Signal Processing,” in Proceedings of the IEEE, Special Issue on “Multimedia Signal Processing”, vol.86, pp. 1155-1202, Jun. 1998
  80. An-Yeu Wu, K. J. R. Liu, and A. Raghupathy, “System Architecture of an Adaptive Reconfigurable DSP Computing Engine,” IEEE Trans. Circuits and Systems for Video Technology, vol. 8, pp. 54-73, Feb. 1998
  81. An-Yeu Wu and K. J. R. Liu, “Split Recursive Least-Squares: Algorithms, Architectures, and Applications,” IEEE Trans. Circuits and Systems Part II: Analog and Digital Signal Processing, vol. 43, pp. 645-658, Sept. 1996

Conference & proceeding papers:

  1. Hung-Yi Cheng, Ching-Chun Liao, and An-Yeu Wu, “Scattering Multi-Connectivity Estimation For Indoor Mmwave Small Cells Under Limited Training Steps,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2019), Brighton, United Kingdom, May 2019
  2. Chieh-Fang Teng, Chen-Hsi (Derek) Wu, Andrew Kuan-Shiuan Ho, and An-Yeu (Andy) Wu, “Low-Complexity Recurrent Neural Network-Based Polar Decoder With Weight Quantization Mechanism,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2019), Brighton, United Kingdom, May 2019
  3. Ching-Yao Chou and An-Yeu Wu, “Low-Complexity Compressive Analysis in Sub-Eigenspace for ECG Telemonitoring System,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2019), Brighton, United Kingdom, May 2019
  4. Ting-Wei Sun and An-Yeu (Andy) Wu, “Sparse Autoencoder with Attention Mechanism for Speech Emotion Recognition,” Proc. IEEE International Symposium on AI for Circuits and Systems (AICAS-2019), Hsinchu, Taiwan, Mar. 2019
  5. En-Jui Chang, Abbas Rahimi, Luca Benini, and An-Yeu (Andy) Wu, “Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals,” Proc. IEEE International Symposium on AI for Circuits and Systems (AICAS-2019), Hsinchu, Taiwan, Mar. 2019
  6. Kuan Tung, Po-Kang Liu, Yu-Chuan Chuang, Sheng-Hui Wang, and An-Yeu (Andy) Wu, “Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals,” Proc. IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES’18), Kuching Sarawak, Malaysia, Dec. 2018
  7. Ting-Sheng Chen, Kai-Ni Hou, Yo-Woei Pua, and An-Yeu (Andy) Wu, “Overview of Efficient Compressive Sensing Reconstruction Engines for E-Health Applications,” Proc. of 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT’18), pp. 1-4, Qingdao, China, Nov. 2018
  8. Chieh-Fang Teng, Ching-Chun Liao, Chun-Hsiang Chen, An-Yeu (Andy) Wu, “Polar Feature based Deep Architecture for Automatic Modulation Classification Considering Channel Fading,” in Proc. IEEE Global Conference on Signal and Information Processing (GlobalSIP’18), pp. 554-558, Anaheim, USA, Nov. 2018
  9. Kai-Chieh Hsu, Bo-Hong Cho, Ching-Yao Chou, and An-Yeu (Andy) Wu, “Low-Complexity Compressed Analysis in Eigenspace with Limited Labeled Data for Real-Time Electrocardiography Telemonitoring,” Proc. IEEE Global Conference on Signal and Information Processing (GlobalSIP’18), pp. 459-463, Anaheim, USA, Nov. 2018
  10. Sheng-Hui Wang, Huai-Ting Li, and An-Yeu (Andy) Wu, “Entropy-Assisted Emotion Recognition of Valence and Arousal Using XGBoost Classifier,” Proc. 14th International Conference on Artificial Intelligence Applications and Innovations (AIAI’18), pp. 249-260, Greece, May 2018
  11. Kai-Ni Hou, Ting-Sheng Chen, Hung-Chi Kuo, Tzu-Hsuan Chen, and An-Yeu (Andy) Wu, “Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018), Calgary, Canada, Apr. 2018
  12. Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu (Andy) Wu, “A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring,” Proc. IEEE International Solid-State Circuits Conference (ISSCC), pp. 226-228, San Francisco, CA, USA, Feb. 2018
  13. Sheng-Hui Wang, Huai-Ting Li, An-Yeu Andy Wu, “Error-Resilient Reconfigurable Boosting Extreme Learning Machine for ECG Telemonitoring Systems,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS-2018), pp. 1-5, Florence, Italy, 2018
  14. An-Yeu (Andy) Wu, Kun-Chih (Jimmy) Chen, and Chih-Hao Chao, “Thermal/Traffic Mutual-Coupling Co-simulation Platform for 3D Network-on-Chip (NoC) Designs,” Proc. International Workshop on Network on Chip Architectures (NoCArc'17), MA, USA, Oct. 2017
  15. Chieh-Fang Teng, Ching-Chun Liao, Hung-Yi Cheng, An-Yeu (Andy) Wu, “Reliable Compressive Sensing (CS)-based Multi-User Detection with Power-based Zadoff-Chu Sequence Design,” IEEE Workshop on Signal Processing Systems (SiPS-2017), Lorient, France, Oct. 2017
  16. Meng-Ya Tsai, Ching-Yao Chou, An-Yeu (Andy) Wu, “Robust Compressed Analysis Using Subspace-based Dictionary for ECG Telemonitoring Systems,” IEEE Workshop on Signal Processing Systems (SiPS-2017), Lorient, France, Oct. 2017
  17. En-Jui Chang, and An-Yeu (Andy) Wu, “ Overview of High-Efficiency Ant Colony Optimization (ACO)-based Adaptive Routings for Traffic Balancing in Network-on-Chip Systems,” in Proc. IEEE 12th International Conference on ASIC (ASICON-2017), Guiyang, China, Oct. 2017
  18. Ching-Che Wang, Yi-Ta Chen, Ding-Yuan Lee, Sheng-Chun Kao, An-Yeu (Andy) Wu, “Profiling and SW/HW Co-design for Efficient SDN/OpenFlow Data Plane Realization,” IEEE International Conference on Electronics Information and Emergency Communication (ICEIEC), pp. 438-443, Macau, China, Jul. 2017
  19. Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, An-Yeu (Andy) Wu, “Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine,” Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’17), pp. 20-24, Hsinchu, Taiwan, Apr. 2017
  20. Hung-Chi Kuo, Yu-Min Lin, An-Yeu (Andy) Wu, “Compressive Sensing Based ECG Monitoring With Effective AF Detection,” IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2017), pp. 1008-1012, New Orleans, USA, Mar. 2017
  21. Hung-Yi Cheng, Ching-Chun Liao, An-Yeu (Andy) Wu, “Progressive Channel Estimation for Ultra-Low Latency Millimeter-wave Communications,” IEEE Global Conference on Signal and Information Processing, pp. 610-614, Greater Washington, D.C., USA, Dec. 2016
  22. Cheng-Rung Tsai, Chiang-Hen Chen, Yu-Hsin Liu, An-Yeu (Andy) Wu, “Joint Spatially Sparse Channel Estimation for Millimeter-wave Cellular Systems,” IEEE Global Conference on Signal and Information Processing, pp. 605-609, Greater Washington, D.C., USA, Dec. 2016
  23. Shih-Ming Shan, Sung-Chun Tang, Pei-Wen Huang, Yu-Min Lin,Wei-Han Huang, Dar-Ming Lai, An-Yeu Wu, “Reliable PPG-based Algorithm in Atrial Fibrillation Detection,” IEEE BioMedical Circuits and Systems Conference, pp. 340-343, Shanghai, China, Oct. 2016
  24. Chien-Sheng Wu, Chiang-Hen Chen, Cheng-Rung Tsai, and An-Yeu (Andy) Wu, “Joint RF/Baseband Grouping-based Codebook Design for Hybrid Beamforming in mmWave MIMO Systems,” IEEE Conference on Signal Processing, Communications and Computing (ICSPCC2016), pp. 1-6, Hong kong, China, Aug. 2016
  25. Yu-Hsin Liu, Chiang-Hen Chen, Cheng-Rung Tsai, and An-Yeu (Andy) Wu, “Multilevel-DFT based Low-Complexity Hybrid Precoding for Millimeter Wave MIMO Systems,” IEEE Conference on Signal Processing, Communications and Computing (ICSPCC2016), pp. 1-5, Hong kong, China, Aug. 2016
  26. Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu (Andy) Wu, “Filter-Based Dual-Voltage Architecture for Low-Power Long-Word TCAM Design,” IEEE Int. Conf. Intelligent Green Building and Smart Grid (IGBSG-2016), pp. 165-16, Prague,Czech Republic, Jun. 2016
  27. Yu-Min Lin, Hung-Chi Kuo, and An-Yeu (Andy) Wu, “Robust LMS-based Compressive Sensing Reconstruction Algorithm for Noisy Wireless Sensor Networks,” IEEE Int. Conf. Intelligent Green Building and Smart Grid (IGBSG-2016), pp. 1-5, Prague,Czech Republic, Jun. 2016
  28. Ching-Yao Chou, Yi-Chieh Ho, Huai-Ting Li, and An-Yeu (Andy) Wu, “Sniper-TEVR: Core-Variation Simulation Platform with Register-Level Fault Injection for Robust Computing in CMP System,” VLSI Design, Automation, and Test (VLSI-DAT’16), pp. 1-4, Hsinchu, Taiwan, Apr. 2016
  29. Jie-Fang Zhang, Jing Geng, Yu-Min Lin, and An-Yeu (Andy) Wu, “Low Memory-Cost Scramble Methods for Constructing Deterministic CS Matrix,” IEEE Workshop on Signal Processing Systems (SiPS-2015), pp. 1-6, Hangzhou, China, Oct. 2015
  30. Jiachen Liu, Hung-Yi Cheng, Ching-Chun Liao, An-Yeu (Andy) Wu, “Scalable Compressive Sensing-Based Multi-User Detection Scheme for Internet-of-Things Applications,” IEEE Workshop on Signal Processing Systems (SiPS-2015), pp. 1-6, Hangzhou, China, Oct. 2015
  31. Wei-Ching Chu, Huai-Ting Li, Ching-Yao Chou, An-Yeu (Andy) Wu, “Variation-Aware Core-Level Redundancy Scheme for Reliable DSP Computation in Multi-Core Systems,” IEEE Workshop on Signal Processing Systems (SiPS-2015), pp. 1-5, Hangzhou, China, Oct. 2015
  32. Wei-Lun Hung, Chiang-Hen Chen, Ching-Chun Liao, Cheng-Rung Tsai, An-Yeu (Andy) Wu, “Low-Complexity Hybrid Precoding Algorithm based on Orthogonal Beamforming Codebook,” IEEE Workshop on Signal Processing Systems (SiPS-2015), pp. 1-5, Hangzhou, China, Oct. 2015
  33. Huai-Ting Li, Ding-Yuan, Lee, Kun-Chih Chen, and An-Yeu (Andy) Wu, “An Algorithmic Error-Resilient Scheme for Robust LDPC Decoding,” IEEE Workshop on Signal Processing Systems (SiPS-2015), pp. 1-4, Hangzhou, China, Oct. 2015
  34. Yu-Min Lin, Yi Chen, Hung-Chi Kuo, and An-Yeu Wu, “Compressive sensing based ECG telemonitoring with personalized dictionary basis,” IEEE Biomedical Circuits and Systems Conference (BioCAS-2015), pp. 1-4, Atlanta, USA, Oct. 2015
  35. Pei-Wen Huang, Sung-Chun Tang, Yu-Min Lin, You-Cheng Liu, Wei-Jung Jou, Hsiao-I Jen, Dar-Ming Lai, An-Yeu Wu, “Predicting Stroke Outcomes based on Multi-modal Analysis of Physiological Signals,” IEEE International Conference on Digital Signal Processing (DSP 2015), pp. 454-457, Singapore, Jul. 2015
  36. Cheng-Rung Tsai, Ming-Chun Hsiao, Wen-Chung Shen, An-Yeu (Andy) Wu, and Chen-Mou Cheng, “A 1.96mm2 Low-Latency Multi-Mode Crypto-Coprocessor for PKC-based IoT Security Protocols,” IEEE Int. Symp. Circuits and Systems (ISCAS-2015), pp. 834-837, Lisbon, Portugal, May 2015
  37. Huai-Ting Li, Ding-Yuan, Lee, Kun-Chih Chen, and An-Yeu (Andy) Wu, “An Algorithmic Error-Resilient Scheme for Robust LDPC Decoding,” IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’15), pp. 1-4, Hsinchu, Taiwan, Apr. 2015
  38. Shih-Chieh Lin, En-Jui Chang, Yu-Yin Chen, Hsien-Kai Hsin, and An-Yeu (Andy) Wu, “High Performance Adaptive Routing for Network-on-Chip Systems with Express Highway Mechanism,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2014), pp.1-4, Okinawa, Japan, Nov. 2014
  39. Nai-Shan Huang, Yu-Min Lin, Yi Chen, and An-Yeu (Andy) Wu, “Adaptive Filter-based Reconstruction Engine Design for Compressive Sensing,” IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS-2014), pp.499-502, Okinawa, Japan, Nov. 2014
  40. Pei-Wen Huang, Wei-Jung Jou, Yu-Min Lin, Hsiao-I Jen, Sung-Chun Tang, Dar-Ming Lai, and An-Yeu (Andy) Wu, “Trend-extracted MSE Based on Adaptive Aligned EEMD with Early Termination Scheme,” IEEE Workshop on Signal Processing Systems (SiPS - 2014), pp.162-167, Belfast, UK, Oct. 2014
  41. Wei-Jung Jou, Pei-Wen Huang, Yu-Min Lin, Sung-Chun Tang, Dar-Ming Lai, An-Yeu Wu, “A Stroke Severity Monitoring System Based on Quantitative Modified Multiscale Entropy,” IEEE Biomedical Circuits and Systems Conference (BioCAS-2014), pp.41-44, Lausanne, Switzerland, Oct. 2014
  42. Yu-Min Lin, Yu-Hao Chen, Ming-Han Chung and An-Yeu (Andy) Wu, “High-Throughput QC-LDPC Decoder with Cost-Effective Early Termination Scheme for Non-Volatile Memory Systems,” IEEE Int. Symp. Circuits and Systems (ISCAS-2014), pp.2732-2735, Melbourne, Jun. 2014
  43. Hung-Yi Cheng, Chun-Yuan Chu, Yen-Liang Chen, and An-Yeu Wu, “Robust Decision Feedback Equalizer Scheme by Using Sphere-Decoding,” IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2014), pp.5074-5077, Florence, Italy, May 2014
  44. Yuan-Sheng Lee, Hsien-Kai Hsin, Kun-Chih Chen, En-Jui Chang, and An-Yeu (Andy) Wu, “Thermal-aware Dynamic Buffer Allocation for Proactive Routing Algorithm on 3D Network-on-Chip Systems,” IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’14), pp.191-194, Hsinchu, Taiwan, Apr. 2014
  45. Kun-Chih Chen, Huai-Ting Li, and An-Yeu (Andy) Wu, “LMS-based Adaptive Temperature Prediction Scheme for Proactive Thermal-aware Three-Dimensional Network-on-Chip Systems,” IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT’14), pp.199-202, Hsinchu, Taiwan, Apr. 2014
  46. Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, An-Yeu (Andy) Wu, “Proactive Thermal-Budget-Based Beltway Routing Algorithm for Thermal-Aware 3D NoC Systems,” Int'l Symp. System-on-Chip, pp. 1-4, Tampere, Nov. 2013
  47. Chia-An Lin, Hsien-Kai Hsin, En-Jui Chang, and An-Yeu (Andy) Wu, “ACO-Based Fault-Aware Routing Algorithm for Network-on-Chip Systems,” IEEE Workshop on Signal Processing Systems (SiPS-2013), pp.342-347, Taipei, Oct. 2013
  48. I-Hsuan Lee, Yu-Hao Chen, Nai-Shan Huang, and An-Yeu (Andy) Wu, “Accelerating Motion-Compensated Adaptive Color Doppler Engine on CUDA-Based GPU Platform,” IEEE Workshop on Signal Processing Systems (SiPS-2013), pp.225-230, Taipei, Oct. 2013
  49. Yu-Hao Chen, Kuan-Yu Ho and An-Yeu(Andy) Wu, “VLSI Implementation of Real-Time Motion Compensated Beamforming in Synthetic Transmit Aperture Imaging,” IEEE Int. Symp. Circuits and Systems (ISCAS-2013), Beijing, May 2013
  50. Zih-Ling Liu, Yu-Hao Chen, Cheng-Zhou Zhan, An-Yeu (Andy) Wu, “Motion Artifact Elimination Algorithm with Eigen-based Clutter Filter for Color Doppler Processing,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2013), pp. 1066-1069, Vancouver, Canada, May 2013
  51. Ming-Han Chung, Yu-Min Lin, Cheng-Zhou Zhan, An-Yeu (Andy) Wu, “Cost-Effective Scalable QC-LDPC Decoder Designs for Non-Volatile Memory Systems,” Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2013), pp. 2625-2628, Vancouver, Canada, May 2013
  52. Kun-Chih Chen, Che-Chuan Kuo, Hui-Shun Hung, and An-Yeu (Andy) Wu, “Traffic- and Thermal-aware Adaptive Beltway Routing for Three Dimensional Network-on-Chip Systems,” IEEE International Symposium on Circuits and Systems (ISCAS-2013), Beijing, May 2013
  53. Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu Wu, “Hybrid Path-Diversity-Aware Adaptive Routing with Latency Prediction Model in Network-on-Chip Systems,” IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2013), pp.348-351, Hsinchu, Taiwan, Apr. 2013
  54. Kun-Chih Chen, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Thermal Management Unit with Vertical Throttling Scheme for Proactive Thermal-aware 3D NoC Systems,” in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2013), Apr. 2013
  55. Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung and An-Yeu Wu, “Traffic-Balanced Topology-Aware Multiple Routing Adjustment For Throttled 3D NoC Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 120-124, Oct. 2012
  56. Yi-Hsuan Lin, Cheng-Zhou Zhan, Chun-Yuan Chu and An-Yeu Wu, “A Low-Complexity Grouping FFT-Based Codebook Searching Algorithm In LTE System,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 161-166, Oct. 2012
  57. Kuan-Yu Su, Hsien-Kai Hsin, En-Jui Chang and An-Yeu Wu, “ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 209-214, Oct. 2012
  58. Yu-Hao Chen, Kuan-Yu Ho, Cheng-Zhou Zhan and An-Yeu Wu, “Coherent Image Herding of Inhomogeneous Motion Compensation for Synthetic Transmit Aperture in Ultrasound Image,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2012), pp. 254-257, Oct. 2012
  59. Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu (Andy) Wu, “Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems,” in Proc. IEEE Sixth International Symposium on Embedded Multicore SoCs, Fukushima, Japan, Sept. 2012
  60. Hui-Shun Hung, Kun-Chih Chen, Che-Chuan Kuo and An-Yeu Wu, “Traffic- and Thermal- Balanced Adaptive Beltway Routing in Thermal Aware 3D NoC Systems,” in Proc. 2012 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2012
  61. Zih-Ling Liu, Cheng-Zhou Zhan, and An-Yeu Wu, “Motion Artifact Elimination Algorithm and Architecture with Eigen-based Clutter Filter for Color Doppler Processing,” in Proc. 2012 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2012
  62. Ming-Han Chung, Yu-Min Lin, Cheng-Zhou Zhan, and An-Yeu Wu, “Cost-Effective Scalable QC-LDPC Decoder Designs for Non-Volatile Memory Systems,” in Proc. 2012 VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 2012
  63. Kun-Chih Chen, Chi-Hao Chao, Shu-Yen Lin, Hui-Shung Hung, and An-Yeu (Andy) Wu, “Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2012), pp. 23-25, Apr. 2012
  64. C.-H. Lin, E.-J. Chang, C.-Y. Chen, and A.-Y. Wu, “A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards,” in Proc. IEEE Int. Symp. Integrated Circuits (ISIC), pp. 178-181, Dec. 2011
  65. Cheng-Zhou Zhan, Zih-Ling Liu, and An-Yeu Wu, “Adaptive Thresholding Incorporating Temporal And Spatial Information With Eigen-Based Clutter Filter For Color Doppler Processing In Ultrasonic Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2011), pp. 361-366, Oct. 2011
  66. Tzu-Chu Yin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Transport Layer Assisted Routing for Thermal-Aware 3D Network-on-Chip,” Asia Pacific Signal and Information Processing Association (APSIPA), Oct. 2011
  67. Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, Shu-Yen Lin, An-Yeu Wu, “Multi-Pheromone ACO-based Routing in Network-on-Chip System Inspired by Economic Phenomenon,” in 24th IEEE International SOC Conference (SOCC-2011), pp. 273-277, Sept. 2011
  68. Chih-Hao Chao, Tzu-Chu Yin, Shu-Yen Lin, An-Yeu Wu, “Transport Layer Assisted Routing for Non-Stationary Irregular Mesh of Thermal-Aware 3D Network-on-Chip Systems,” in 24th IEEE International SOC Conference (SOCC-2011), pp. 284-289, Sept. 2011
  69. Tzu-Chu Yin, Chih-Hao Chao, Hui-Shun Hung, Shu-Yen Lin and An-Yeu Wu, " Design of Transport Layer Assisted Routing for Thermal-Aware 3D Network-on-Chip, “Design of Transport Layer Assisted Routing for Thermal-Aware 3D Network-on-Chip,” Proc. 2011 VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2011
  70. Yen-Liang Chen, Shao-Wei Feng, Cheng-Zhou Zhan and An-Yeu Wu, “Channel Shortening Equalizer with Robust TIR Quality Controlled for OFDM Systems,” in Proc. 2011 VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2011
  71. Cheng-Zhou Zhan, Zih-Ling Liu and An-Yeu Wu, “Adaptive Thresholding with Temporal and Spatial Information on Eigen-based Clutter Filter for Ultrasound Doppler Processing,” in Proc. 2011 VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2011
  72. Shu-Yen Lin, Tzu-Chu Yin, Hao-Yu Wang and An-Yeu Wu, “Traffic-and Thermal-Aware Routing for Throttled Three-Dimensional Network-on-Chip Systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2011), pp. 320-323, Apr. 2011
  73. Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Yeu Wu, “Regional ACO-based Routing for Load-Balancing in NoC Systems,” IEEE Second World Congress on Nature and Biologically Inspired Computing (NaBIC-2010), pp. 377-383, Dec. 2010
  74. Cheng-Zhou Zhan, Kai-Ting Chang, Yu-Hao Chen, Pai-Chi Li, and An-Yeu Wu, “Motion-Tracking Adaptive Persistence and Adaptive-Size Median Filter for Color Doppler Processing in Ultrasonic Systems on Multi-core Platform,” Proc. IEEE Conference on Biomedical Circuits and Systems (BioCAS-2010), Nov. 2010
  75. Chun-Yuan Chu, Chih-Hao Chao, Min-An Chao, and An-Yeu Wu, “Multi-Prediction Particle Filter for Efficient Memory Utilization,” Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010) , pp. 295-298, Oct. 2010
  76. Chih-Hao Chao, Chun-Yuan Chu, Min-An Chao, and An-Yeu Wu, “Cost-Effective Constrained Particle Filter For Indoor Location,” Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 290-294, Oct. 2010
  77. Min-An Chao, Chun-Yuan Chu, Chih-Hao Chao, and An-Yeu Wu, “Efficient Parallelized Particle Filter Design on CUDA,” Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 299-304, Oct. 2010
  78. Kai-Ting Chang, Cheng-Zhou Zhan, and An-Yeu Wu, “Joint-Decision Adaptive Clutter Filter and Motion-Tracking Adaptive Persistence for Color Doppler Processing in Ultrasonic Systems,” Proc. IEEE Workshop on Signal Processing Systems (SiPS-2010), pp. 249-253, Oct. 2010
  79. Yen-Liang Chen, Ting-Jyun Jheng, Cheng-Zhou Zhan, and An-Yeu Wu, “A 2.17 mm2 125mW Reconfigurable SVD Chip for IEEE 802.11n System,” Proc. IEEE Conference on European Solid-State Circuits (ESSCIRC-2010), pp. 534-537, Sept. 2010
  80. Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, and An-Yeu Wu, “Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems,” Proc. ACM/IEEE int. Sym. Networks-on-Chip (NOCS), pp.223-230, May 2010
  81. Kai-Yuan Jheng, Chih-Hao Chao, Hao-Yu Wang, and An-Yeu Wu, “Traffic-thermal mutual-coupling co-simulation platform for three-dimensional Network-on-Chip,” Proc. int. Sym. VLSI Design Automation and Test (VLSI-DAT), pp.135-138, Apr. 2010
  82. Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, and An-Yeu Wu, “A Channel-Adaptive Early Termination strategy for LDPC decoders,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2009), pp. 226-231, Finland, Oct. 2009
  83. Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, and An-Yeu Wu, “A Triple-Mode LDPC Decoder Design for IEEE 802.11n System,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2009), pp. 2445-2448, Taipei, Taiwan, May 2009
  84. Shu-Yen Lin, Chan-cheng Hsu, and An-Yeu Wu, “A Scalable Built-in Self-Test/Self-Diagnosis Architecture for 2D-mesh Based Chip Multiprocessor Systems,” Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2009), pp. 2317-2320, Taipei, Taiwan, May 2009
  85. Cheng-Zhou Zhan, Kai-Yuan Jheng, Yen-Lian Chen, Ting-Jhun Jheng, and An-Yeu Wu, “High-Convergence-Speed Low-Computation-Complexity SVD Algorithm for MIMO-OFDM Systems,” Proc. IEEE Int. Symp. VLSI Design, Automation, and Test(VLSI-DAT-2009),, pp. 195-198, Hsinchu, Taiwan, Apr. 2009
  86. Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, Chih-Hao Chao, and An-Yeu Wu, “Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor Systems,” Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2009), pp. 72-75, Hsinchu, Taiwan, Apr. 2009
  87. Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, “A 52-mW 8.29mm2 19-mode LDPC Decoder Chip for Mobile WiMAX Applications,” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC-2009), pp. 121-122, Yokohama, JAPAN, Jan. 2009
  88. Xin-Yu Shih, Cheng-Zhou Zhan, and An-Yeu Wu, “A 7.39mm2 76mW (1944, 972) LDPC Decoder Chip for IEEE 802.11n Applications,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2008), pp. 301-304, Fukuoka, JAPAN, Nov. 2008
  89. Chih-Hao Chao, Chun-Yuan Chu and An-Yeu Wu, “Location-Constrained Particle Filter for RSSI-Based Indoor Human Positioning and Tracking System,” n Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), pp. 73-76, DC, USA, Oct. 2008
  90. Chun-Yu Chen, Cheng-Hung Lin and An-Yeu Wu, “High-Throughput Dual-Mode Single/Double Binary Map Processor Design for Wireless WAN,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), pp. 83-87, DC, USA, Oct. 2008
  91. Ting-Jung Lin, Shu-Yen Lin and An-Yeu Wu, “Traffic-Balanced IP Mapping Algorithm for 2D-MESH On-Chip-Networks,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), pp. 200-203, DC, USA, Oct. 2008
  92. Huifei Rao, Jie Chen, Vicky H. Zhao, Woon Tiong Ang, I-Chyn Wey and An-Yeu Wu, “An Efficient Methodology to Evaluate Nanoscale Circuit Fault-tolerance Performance based on Belief Propagation,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008),, pp. 608-611, Seattle, USA, May 2008
  93. Cheng-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, “Low-Power Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008), pp. 736-739, Seattle, USA, May 2008
  94. Yen-Liang Chen,Cheng-Zhou Zhan, and An-Yeu Wu, “Cost-Effective Echo and Next Canceller Designs for 10GBASE-T Ethernet System,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2008), pp. 3150-3153, Seattle, USA, May 2008
  95. Cheng-Hung Lin, Chun-Yu Chen, and An-Yeu Wu, “High-Throughput 12-Mode CTC Decoder for WiMAX Standard,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), pp.216-219, Hsinchu, Taiwan, Apr. 2008
  96. Chun-Yuan Chu, Yu-Chuan Huang, and An-Yeu Wu, “Power Efficient Low Latency Survivor Memory Architecture for Viterbi Decoder,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), pp.228-231, Hsinchu, Taiwan, Apr. 2008
  97. Yen-Liang Chen, Chun-Yu Chen, Kai-Yuan Jheng, and An-Yeu Wu, “A Universal Look-Ahead Algorithm for Pipelining IIR Filters,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), pp.259-262, Hsinchu, Taiwan, Apr. 2008
  98. Tay-Jyi Lin, Chun-Nan Liu, Shau-Yin Tseng, Yuan-Hua Chu, and An-Yeu Wu, “Overview of ITRI PAC Project – from VLIW DSP Processor to Multicore Computing Platform,” n Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2008), pp. 188-191, Hsinchu, Taiwan, Apr. 2008
  99. Cheng-Zhou Zhan, Xin-Yu Shih, and An-Yeu Wu, “High-Performance Scheduling Algorithm for Partially Parallel LDPC Decoder,” in Proc. IEEE Int. Conf. Acoustic, Speech, Signal Processing (ICASSP-2008), pp. 3177-3178, Las Vegas, USA, Mar. 2008
  100. I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu Wu, “A 0.13μm Hardware-Efficient Probabilistic-Based Noise-Tolerant Circuit Design and Implementation with 24.5dB Noise-Immunity Improvement,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2007), pp. 295-298, Jeju, Korea, Nov. 2007
  101. Kai-Yuan Jheng, Yuan-Jyue Chen, and An-Yeu Wu, “Multilevel LINC System Design For Power Efficiency Enhancement,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), pp. 31-34, Shanghai, China, Oct. 2007
  102. Tzu-Hao Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, and An-Yeu Wu, “Reconfigurable Color Doppler DSP Engine For High - Frequency Ultrasonic Image Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), pp. 187-192, Shanghai, China, Oct. 2007
  103. Chun-Yuan Chu, Jyh-Ting Lai, and An-Yeu Wu, “Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based UWB systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), pp. 403-406, Shanghai, China, Oct. 2007
  104. Chi-Li Yu, Tzu-Hao Yu, and An-Yeu Wu, “On The Fixed-Point Properties of Mixed-Scalling-Rotation CORDIC Algorithm,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), pp. 430-435, Shanghai, China, Oct. 2007
  105. Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, and An-Yeu Wu, “Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2007), pp. 493-498, Shanghai, China, Oct. 2007
  106. Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, “A 19-mode 8.29mm2 52-mW LDPC Decoder Chip for IEEE 802.16e System,” in Proc. Int. Symp. VLSI Circuits (SOVC-2007), pp. 16-17, Kyoto, JAPAN, Jun. 2007
  107. Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, and An-Yeu Wu, “A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network,” in Proc. ACM/IEEE Int. Symp. Networks-on-Chip (NOCS-2007), pp. 317-322, Princeton, USA, May 2007
  108. Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, and An-Yeu Wu, “Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), pp. 869-872, New Orleans, USA, May 2007
  109. Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, and Weber Chien, “A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), pp. 869-872, New Orleans, USA, May 2007
  110. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu and Hong Zhao, “Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2007), pp. 1803-1806, New Orleans, USA, May 2007
  111. Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao, and Bosen Tzeng, “Multilevel LINC System Design for Wireless Transmitters,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2007), pp.208 - 211, Hsinchu, TAIWAN, Apr. 2007
  112. I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen and An-Yeu Wu, “A 0.18μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2006), pp. 291-294, Hangzhou, CHINA, Nov. 2006
  113. You-Gang Chen, I-Chyn Wey, and An-Yeu Wu, “A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2006), pp. 295-298, Hangzhou, CHINA, Nov. 2006
  114. Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, and An-Yeu Wu, “Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 62-65, Banff, CANADA, Oct. 2006
  115. Fan-Min Li, Cheng-Hung Lin, and An-Yeu Wu, “A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 89-94, Banff, CANADA, Oct. 2006
  116. Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, and Wen-Chiang Chen, “A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-WideBand Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 165-170, Banff, Canada, Oct. 2006
  117. Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, and Wen-Chiang Chen, “A Low Cost Packet Detector in OFDM-based Ultra-WideBand systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 171-176, Banff, CANADA, Oct. 2006
  118. Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, and An-Yeu Wu, “A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10Gbase-T Ethernet System,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 330-333, Banff, CANADA, Oct. 2006
  119. Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, and An-Yeu Wu, “On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2006), pp. 426-431, Banff, CANADA, Oct. 2006
  120. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, and An-Yeu Wu, “A Portable All-Digital Pulsewidth Control Loop for SOC Applications,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), pp. 3165-3168, Island of Kos, GREECE, May 2006
  121. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu Wu, “A Frequency Estimation Algorithm for ADPLL Designs with Two-cycle Lock-in Time,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), pp. 4082-4085, Island of Kos, GREECE, May 2006
  122. Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, and Hen-Wai Tsao, “DSP Engine Design for LINC Wireless Transmitter Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2006), pp. 2593-2596, Island of Kos, GREECE, May 2006
  123. Fan-Min Li, and An-Yeu Wu, “A New Stopping Criterion for Efficient Early Termination in Turbo Decoder Designs,” in Proc. 2005 Int. Symp. Intelligent Signal Processing and Communication Systems (ISPACS-2005), pp. 585-588, Hong Kong, CHINA, Dec. 2005
  124. Chung-Chun Chen, Hung-Yang Ko, Yi-Chiuan Wang, Hen-Wai Tsao, Kai-Yuan Jheng, and An-Yeu Wu, “Polar Transmitter for Wireless Communication System,” in Proc. 2005 Int. Symp. Intelligent Signal Processing and Communication Systems (ISPACS-2005), pp. 613-616, Hong Kong, CHINA, Dec. 2005
  125. Cheng-Hung Lin, Fan-Min Li, Xin-Yu Shi, and An-Yeu Wu,, “A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC-2005), pp. 221-224, Hsinchu, TAIWAN, Nov. 2005
  126. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, “Ultra Low-Cost 3.2Gb/s Optical-Rate Reed Solomon Decoder IC Design,” in Proc. Student Design Contest of IEEE Asian Solid-State Circuits Conf. (A-SSCC-2005), pp. 533-536, Hsinchu, TAIWAN, Nov. 2005
  127. Hung-Yang Ko, Yi-Chiuan Wang, and An-Yeu Wu, “Digital Signal Processing Engine Design For Polar Transmitter,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), pp. 6026-6029, Kobe, JAPAN, May 2005
  128. Tsung-Han Tsai, Cheng-Hung Lin, and An-Yeu Wu, “A Memory-Reduced Log-Map Kernel For Turbo Decoder,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), pp. 1032-1035, Kobe, JAPAN, May 2005
  129. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu Wu, “A Scalable DCO Design for Portable ADPLL Designs,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), pp. 5449-5452, Kobe, JAPAN, May 2005
  130. I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, and An-Yeu Wu, “A 2Gb/S High-Speed Scalable Shift-Register Based On-Chip Serial Communication Design for Soc Applications,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2005), pp. 1074-1077, Kobe, JAPAN, May 2005
  131. Kai-Yuan Jheng, Tsung-Han Wu, Yi-Chiuan Wang, Jih-Chiang Yeo, Yu-Ju Cho, and An-Yeu Wu, “A DVB-T Baseband Demodulator Design Based on Multimode Silicon IPs A DVB-T Baseband Demodulator Design based on Multimode Silicon IPs,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2005), pp. 49-52, Hsinchu, TAIWAN, Apr. 2005
  132. Chih-Hsiu Lin and An-Yeu Wu, “Low-Cost Decision Feedback Equalizer (DFE) Design for Giga-Bit Systems,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2005), vol. 3, pp. 100, Philadelphia, USA, Mar. 2005
  133. Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, “Unified Convolutional/Turbo Decoder Architecture Design Based on Triple-Mode MAP/VA Kernel,” in Proc. IEEE Asia-Pacific Conf. Circuits and Systems (APCCAS 2004), vol.2, pp. 1073-1076, Tainan, Taiwan, Dec. 2004
  134. Chih-Hsiu Lin and An-Yeu Wu, “Robust Decision Feedback Equalizer Design using Soft-Threshold-based Multi-layer Detection Scheme,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), pp. 118-123, Austin, USA, Oct. 2004
  135. Jih-Chiang Yeo, Huai-Yi Hsu, and An-Yeu Wu, “A Scalable Reed-Solomon Decoding Processor based on Unified Finite-field Processing Element Design,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), pp. 118-123, Austin, USA, Oct. 2004
  136. Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, “Triple-Mode MAP/VA Timing Analysis for Unified Convolutional/Turbo Decoder Design,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2004), pp. 280-285, Austin, USA, Oct. 2004
  137. I-Chyn Wey, Hwang-Cherng Chow, You-Gang Chen, and An-Yeu Wu, “A Fast and Power-Saving Self-Timed Manchester Carry-Bypass Adder for Booth Multiplier-Accumulator Design,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), pp. 50-53, Fukuoka, Japan, Aug. 2004
  138. Shyh-Jye Jou, Kai-Yuan Jheng, Hsiao-Yun Chen, An-Yeu Wu, “Multiplierless Multirate Decimator/Interpolator Module Generator,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), pp. 58-61, Fukuoka, Japan, Aug. 2004
  139. Huai-Yi Hsu, Jih-Chiang Yeo, and An-Yeu Wu, “Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), pp. 314-317, Fukuoka, Japan, Aug. 2004
  140. Kai Huang, Fan-Min Li, Pei-Ling Shen, and An-Yeu Wu, “VLSI Design of Dual-mode Viterbi/Turbo Decoder for 3GPP,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), vol. II, 773-776, Vancouver, May 2004
  141. Hsiu-ping Lin, Nancy F. Chen, Jyh-Ting Lai, and An-Yeu Wu, “1000BASE-T Gigabit Ethernet Baseband DSP IC Design,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), vol. IV, pp. 401-404, Vancouver, May 2004
  142. Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, and An-Yeu Wu, “Least Squares Approximation-based ROM-free Direct Digital Frequency Synthesizer,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), vol. II, pp. 701-704, Vancouver, May 2004
  143. Kai-Yuan Jheng, Shyh-Jye Jou, and An-Yeu Wu, “A Design Flow for Multiplierless Linear-phase FIR Filters: From System Specifications to Verilog Code,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2004), vol. V, pp. 293-296, Vancouver, May 2004
  144. Pen-Hsin Chen, Kai-Huang, Nai-Hsuan Hsueh, and An-Yeu Wu, “Dual-Mode Convolutional/SOVA Based Turbo Code Decoder VLSI Design for Wireless Communication Systems,” in Proc. IEEE International SOC Conference (formerly IEEE International ASIC/SOC Conference), pp. 369-372, Portland, Sept. 2003
  145. Jyh-Ting Lai, An-Yeu Wu, and Cheng-Chung Yeh, “A Novel Multipath Matrix Algorithm for Exact Room Response Identification in Stereo Echo Cancellation,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2003), pp. 236-240, Seoul, Korea, Aug. 2003
  146. Jen-Chih Kuo, Ching-Hua Wen, and An-Yeu Wu, “Implementation of a Programmable 64~2048-Point FFT/IFFT Processor for OFDM-based Communication Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2003), vol. II, pp. 121-124, Bangkok, May 2003
  147. Zhi-Xiu Lin and An-Yeu Wu, “Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) Algorithm and Architecture for Scaling-Free High-Performance Rotational Operations,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2003), vol. II, pp. 653-656, Hong Kong, Apr. 2003
  148. An-Yeu Wu, I-Hsien Lee, and Cheng-Shing Wu, “Angle Quantization Approach for Lattice IIR Filter Implementation and Its Trellis De-Allocation Algorithm,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2003), vol. II, pp. 673-676, Hong Kong, Apr. 2003
  149. Meng-Da Yang and An-Yeu Wu, “High-performance Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer Scheme,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2002), pp. 121-126, San Diego, USA, Oct. 2002
  150. Huai-Yi Hsu and An-Yeu Wu, “VLSI Design of A Reconfigurable Multi-mode Reed-Solomon Codec for High-Speed Communication Systems,” in Proc. IEEE Asia Pacific Conf. on ASICs (AP-ASIC 2002), pp. 359-362, Taipei, ROC, Aug. 2002
  151. Cheng-Shing Wu and An-Yeu Wu, “A Novel Cost-Effective Multi-path Adaptive Interpolated FIR (IFIR)-Based Echo Canceller,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2002), vol. 5, pp. 453-456, Phoenix, May 2002
  152. Meng-Da Yang and An-Yeu Wu, “A New Pipelined Adaptive DFE Architecture with Improved Convergence Rate,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2002), pp. 213-216, Phoenix, May 2002
  153. Sheng-Feng Wang, Huai-Yi Hsu, and An-Yeu Wu, “A Very Low-Cost Multi-mode Reed Solomon Decoder based on Peterson-Gorenstein-Zierler Algorithm,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2001), pp. 37-48, Antwerp, Belgium, Sept. 2001
  154. Chih-Chi Wang and An-Yeu Wu, “A Cost-effective TEQ Algorithm for ADSL Systems,” in Proc. IEEE International Conf. on Communications (ICC-2001), vol. 2, pp. 398-402, Helsinki, Finland, Jun. 2001
  155. Chi-li Yu and An-Yeu Wu, “An Improved Time-Recursive Lattice Structure for Low-Latency IFFT Architecture in DMT Transmitter,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2001), vol. 4, pp. 250-253, Sydney, May 2001
  156. Cheng-Shing Wu and An-Yeu Wu, “A Novel Trellis-based Searching Scheme for EEAS-based CORDIC Algorithm,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), Salt Lake City, vol. 2, pp. 1229-1232, May 2001
  157. An-Yeu Wu and Cheng-Shing Wu, “A Unified Design Framework for Vector Rotational CORDIC Family Based on Angle Quantization Process,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), vol. 2, pp. 1233-1236, Salt Lake City, May 2001
  158. I-Hsien Lee, Ceng-Shing Wu, and An-Yeu Wu, “Cost-Efficient Multiplier-less FIR Filter Structure Based on Modified DECOR Transformation,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2001), vol. 2, pp. 1065-1068, Salt Lake City, May 2001
  159. Cheng-Shing Wu and An-Yeu Wu, “A Novel Rotational VLSI Architecture Based on Extended Elementary Angle Set CORDIC Algorithm,” in Proc. IEEE Asia Pacific Conf. on ASICs (AP-ASIC 2000), pp.111-114, Cheju, Korea, Aug. 2000
  160. Cheng-Shing Wu and An-Yeu Wu, “Modified Vector Rotational CORDIC (MVR-CORDIC) Algorithm and Its Application to FFT,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2000), pp.IV.529-532, Geneva, May 2000
  161. Jye-Jong Leu and An-Yeu Wu, “Design Methodology for Booth-encoded Montgomery Module Design for RSA Cryptosystem,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2000), pp. V.357-360, Geneva, Mar. 2000
  162. Jye-Jong Leu and An-Yeu Wu, “A Scalable Low-Complexity Digit-Serial VLSI Architecture for RSA Cryptosystem,” in Proc. IEEE Workshop on Signal Processing Systems (SiPS-99), pp. 586-595, Taipei, Oct. 1999
  163. Cheng-Shing Wu and An-Yeu Wu, “A Novel Multirate Adaptive FIR Filtering Algorithm and Architecture,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-99), pp.IV.1849-1852, Phoenix, Mar. 1999
  164. An-Yeu Wu,, Tsun-Shan Chan, and Bowen Wang, “A Fast Algorithm for Reduced-complexity Programmable DSP Implementation of the IFFT/FFT in DMT Systems,” in IEEE 1998 Global Telecommunications Conference (GLOBECOM-98), pp. 471-476, Sydney, Nov. 1998
  165. An-Yeu Wu, and Tsun-Shan Chan, “Computationally Efficient Fast Algorithm and Architecture for the IFFT/FFT in DMT/OFDM Systems,” in IEEE Workshop on Signal Processing Systems (SiPS-98), pp.356-365, Boston, Oct. 1998
  166. An-Yeu Wu, and Tsun-Shan Chan, “Cost-efficient Parallel Lattice VLSI Architecture for the IFFT/FFT in DMT Transceiver Technology,” in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-98), pp.VI.3517-3520, Seattle, May 1998
  167. An-Yeu Wu, and Kuo-Fuo Hwang, “Optimal Fixed-point VLSI Structure of a Floating-point based Filter Design,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-98), pp.V.375-378, Monterey, May 1998
  168. An-Yeu Wu, and Cheng-Shing Wu, “Transform-domain Delayed LMS Algorithm and Architecture,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-98), pp.V.194-197, Monterey, May 1998
  169. An-Yeu Wu, K. J. R. Liu, Z. Zhang, K. Nakajima, and A. Raghupathy, “Low-Power DSP System Design Using Multirate Approach,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-96), pp.IV.292-295, Atlanta, May 1996
  170. An-Yeu Wu, K. J. R. Liu, A. Raghupathy, and S.-C. Liu, “Parallel Programmable Video Co-processor Design,” in Proc. IEEE Int. Conf. on Image Processing (ICIP-95), pp. I.61-64, Washington D.C., Oct. 1995
  171. An-Yeu Wu and K. J. R. Liu, “Algorithm-Based Low-Power Transform Coding Architectures,” n Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-95), pp. 3267-3270, Detroit, May 1995
  172. A.-Y.Wu and K. J. R. Liu, “A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture based on Backward Chebyshev Recursion,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-94), pp.4.155-4.158, London, May 1994
  173. An-Yeu Wu and K. J. R. Liu, “A Universal Fast Algorithm and Architecture for Nonstructured RLS Filtering,” in Proc. Conf. on Information Sciences and Systems., (CISS-93), pp.235-240, John Hopkins University, 1993
  174. K. J. R. Liu and An-Yeu Wu, “A Multi-layer 2-D Adaptive Filtering Architecture based on McClellan Transformation,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-93), pp. 1999-2002, Chicago, 1993
  175. a, “a,” a

Books:

  1. Kun-Chih Chen, Chi-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Chapter 12: Thermal- and Traffic-Aware Routing for 3D NoC Systems,” in Routing Algorithms in Networks-on-Chip (M. Palesi and M. Daneshtalab eds.), Springer, pp. 307-33 pages, Nov. 2013
  2. Shu-Yen Lin and An-Yeu Wu, “Chapter 4: Routing Algorithms for Irregular Mesh-based Network-on-Chip,” in “Multi-core Embedded System (Georgios Kornaros eds.), CRC Press, pp.111-154 pages, Apr. 2010
  3. K. J. R. Liu and A.-Y. Wu,, “Chapter 18: Systolic RLS Adaptive Filtering,” in Digital Signal Processing for Multimedia Systems, Part II: Programmable and Custom Architectures and Algorithms (K. K. Parhi, Marcel Dekker, Inc. (New York),, pp. 487-51 pages, 1999
  4. An-Yeu Wu, K. J. R. Liu, Z. Zhang, K. Nakajima, S.-C. Liu, and A. Raghupathy, “Algorithm-Based Low-Power Digital Signal Processing System Design: Methodology and Verification,” in VLSI Signal Processing VIII (T. Nishitani and K. K. Parhi, eds.), IEEE Press, pp.277-286 pages, 1995
  5. K. J. R. Liu and An-Yeu Wu, “Algorithms and Architectures for Split Recursive Least Squares,” in VLSI Signal Processing VII (J. Rabaey, P.M. Chau, and J. Eldon, eds.), IEEE Press, pp.460-469 pages, 1994

Patents:

  1. An-Yeu Wu, Yu-Min Lin, Hung-Chi Kuo, and Yi Chen, “基於個人化基底的壓縮感知系統及其方法,” USA Patent, No. 9,667,456 B2, May 2017
  2. Cheng-Rung Tsai, An-Yeu Wu, Shih-Lun Huang, Chih Yuan, and Hsu-Ming Chuang, “Multi-channel sensing system and operating method thereof,” USA Patent, No. 9,442,617, Sept. 2016
  3. Kun Chih Chen, An-Yeu Wu, and Huai-Ting Li, “溫度預測系統及其方法,” 中華民國專利發明第I544318號, Aug. 2016
  4. An-Yeu Wu, Wen-Chung Shen, and Hsiao-I Jen, “具低延遲性的經驗模態分解法之信號分解系統及其方法,” 中華民國專利發明第I529541號, Apr. 2016
  5. Yen-Liang Chen, Shao-Wei Feng, Cheng-Zhou Zhan, and An-Yeu Wu, “Method and apparatus for performing channel shortening equalization with frequency notch mitigation,” USA Patent, No. 9,065,690, Jun. 2015
  6. Ming-Chia Tsai, An-Yeu Wu, Paichi Li, Chen-Jo Chan, and Yu-Hao Chen, “Detection System and Signal Processing Method Thereof,” 15. CHINA, Patent No. CN102613989B, Jul. 2014
  7. Cheng-Zhou Zhan, Yen-Liang Chen, Ting-Jhun Jheng and An-Yeu Wu, “Singular Value Decomposition Method and Device,” 14. ROC (Taiwan) Patent, No. I393394, Apr. 2013
  8. Xin-Yu Shih and An-Yeu Wu, “Programmable LDPC Code Decoder and Decoding Method Thereof,” 13. ROC (Taiwan) Patent, No. I380598, Dec. 2012
  9. Cheng-Zhou Zhan, Yen-Liang Chen, Ting-Jhun Jheng and An-Yeu Wu, “Singular value decomposing method and related singular value decomposing device,” USA Patent, No. 8,321,488, Nov. 2012
  10. Cheng-Ming Chen, Yen-Liang Chen, Pang-An Ting and An-Yu Wu, “Codebook Searching Apparatus and Method Thereof,” 12. ROC (Taiwan) Patent, No. I377802, Nov. 2012
  11. Xin Yu Shih and An-Yeu Wu, “Programmable LDPC code decoder and decoding method thereof,” US Patent No. 8,296,622, Oct. 2012
  12. Yen-Liang Chen, Cheng-Ming Chen, Pang-An Ting, and An-Yeu Wu, “Codebook searching apparatus and thereof,” US Patent No. 8,275,060, Sept. 2012
  13. Cheng-Hung Lin and An-Yu Wu, “Method and apparatus for turbo code decoding,” US Patent No. 8,230,311, Jul. 2012
  14. Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao and Posen Tseng, “Multilevel LINC Transmitter,” 11. ROC (Taiwan) Patent, No. I349445, Sept. 2011
  15. Yuan-Jyue Chen, Kai-Yuan Jheng and An-Yeu Wu, “Multilevel LINC Transmitter,” 9. ROC (Taiwan) Patent, No. I339972, Apr. 2011
  16. Cheng-Hung Lin and and An-Yeu Wu, “Method and Apparatus for Convolutional Turbo Decoding,” 10. ROC (Taiwan) Patent, No. I339956, Apr. 2011
  17. Yuan-Jyue Chen, Kai-Yuan Jheng, and An-Yeu Wu, “Multilevel LINC Transmitter,” US Patent No. 7,826,553, Nov. 2010
  18. Yuan-Jyue Chen, Kai-Yuan Jheng, An-Yeu Wu, Hen-Wai Tsao, and Posen Tseng, “Multilevel LINC Transmitter,” US Patent No. 7724839, May 2010
  19. Muh-Tian Shiue, Chorng-Kuang Wang, Chih-Feng Wu and An-Yeu Wu, “Discrete Multi-Tone System Having DHT-Based Frequency-Domain Equalizer,” 8. ROC (Taiwan) Patent, No. I325256, May 2010
  20. Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang, and An-Yeu Wu, “On-line step-size calculation using signal power estimation and tone grouping of the frequency-domain equalizer for DMT-based transceiver,” US Patent No. 7,602,844, Oct. 2009
  21. Chih-Feng Wu, Muh-Tian Shiue, Chorng-Kuang Wang, and An-Yeu Wu, “Discrete multi-tone System having DHT-based frequency-domain equalizer,” US Patent No. 7,545,871, Jun. 2009
  22. Meng-Da Yang , An-Yeu Wu, and Murphy Chen, “Predicted parallel branch slicer and slicing method thereof,” US Patent No. 7,317,755, Jan. 2008
  23. Meng-Da Yang , An-Yeu Wu, Chih-Hsiu Lin, “Soft-threshold-based multi-layer decision feedback equalizer and decision method,” US Patent No. 7,483,482, Jan. 2008
  24. Cheng-Shing Wu and An-Yeu Wu, “Methods and systems for providing multi-path echo cancellation,” US Patent No. 7,200,221, Apr. 2007
  25. 林志修、吳安宇, “多層軟性決策回饋等化器及決策方法,” 中華民國專利發明第I258085號, Jul. 2006
  26. Cheng-shing Wu, Chia-Ho Pan, and An-Yeu Wu, “CORDIC Method and Architecture Applied in Vector Rotation,” US Patent No. 7,047,269, May 2006
  27. I-Hsien Lee, Cheng-Shing Wu, and An-Yeu Wu, “Method for Implementing a Multiplier-less FIR Filter,” US Patent No. 7,054,896, May 2006
  28. Chi-Li Yu and An-Yeu Wu, “Time-recursive Lattice Structure for IFFT in DMT Application,” US Patent No. 6,985,919, Jan. 2006
  29. 楊孟達、吳安宇、陳任凱, “預測並行分支量階器與量階方法,” 中華民國專利發明第I237789號, Aug. 2005
  30. 吳政勳、吳安宇, “提供多路徑回聲消除之方法與系統,” 中華民國專利發明第I220603號, Aug. 2004
  31. 吳政勳、潘佳河、 吳安宇, “應用在向量旋轉器之座標旋轉數位計算器運算方法及架構,” 中華民國專利發明第583579號, Apr. 2004
  32. Chih-Chi Wang, An-Yeu Wu, Bor-Min Wang, “用於同步數位系統等化混合時域及頻域之方法,” 韓國專利發明第428611號, Apr. 2004
  33. Meng-Da Yang and An-Yeu Wu, “Fast Convergent Pipelined Adaptive Decision Feedback Equalizer Using Post-cursor Processing Filter,” US Pattern No. 6,697,424, Feb. 2004
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