盧奕璋教授的著作列表 - Publication List of Yi-Chang Lu

Publication List of 盧奕璋 Yi-Chang Lu

Journal articles & book chapters:

  1. Guani Wu, Yu-Cheng Li, Yi-Chang Lu, Ker-Chau Li, Shinsheng Yuan, “GPU Accelerated Liquid Association (GALA),” Statistics and Its Interface, Vol. 13, No. 1, 119~125, Jan. 2020
  2. Yu-Cheng Li, Yi-Chang Lu, “BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 13, No. 6, 1771~1782, Dec. 2019
  3. Chiu-Chih Chou, Shih-Shiuan Weng, Yi-Chang Lu, Tzong-Lin Wu, “EMI-Reduction Coding Based on 8b/10b,” IEEE Transactions on Electromagnetic Compatibility, Vol. 61, No. 4, 1007~1014, Aug. 2019
  4. Chun-Chang Yu, Pei-Chun Lin, Yi-Chang Lu, Charlie Chung-Ping Chen, “Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems,” Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 17, No. 3, pp. 031202:1-11, Jul. 2018
  5. Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Hsieh-Hung Hsieh, Ming-Hsien Tsai, Sally Liu, Tzong-Lin Wu, “EGB-based grid-type PDN on interposer for SSN mitigation in mixed-signal system-in-package,” IEEE Microwave and Wireless Components Letters, Vol. 27, No. 12, pp. 1053-1055, Dec. 2017
  6. Yi-An Hsu, Chi-Hsuan Cheng, Yi-Chang Lu, Tzong-Lin Wu, “An accurate and fast substrate noise prediction method with octagonal TSV model for 3-D ICs,” IEEE Trans. Electromagnetic Compatibility, Vol. 59, No. 5, pp. 1549-1557, Oct. 2017
  7. Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu, “Efficient layout data compression algorithm and its low-complexity, high-performance hardware decoder implementation for multiple electron-beam direct-write systems,” J. of Micro/Nanolithography, MEMS, and MOEMS, Vol. 14, No. 3, pp. 031212:1-15, Jul. 2015
  8. Chi-Hsuan Cheng, Tai-Yu Cheng, Cheng-Han Du, Yi-Chang Lu, Yih-Peng Chiou, Sally Liu, Tzong-Lin Wu, “An equation-based circuit model and its generation tool for 3-D IC power delivery networks with an emphasis on coupling effect,” IEEE Trans. Components, Packaging and Manufacturing Technology, Vol. 4, No. 6, pp. 1062-1070, Jun. 2014
  9. Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James C.-M. Li, Krishnendu Chakrabarty, “Testing of TSV-induced small delay faults for 3-D integrated circuits,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 3, pp. 667-674, Mar. 2014
  10. Chuen-De Wang, Yu-Jen Chang, Yi-Chang Lu, Peng-Shu Chen, Wei-Chung Lo, Yih-Peng Chiou, and Tzong-Lin Wu, “ABF-based TSV arrays with improved signal integrity on 3-D IC/interposers: equivalent models and experiments,” IEEE Trans. Components, Packaging and Manufacturing Technology, Vol. 3, No. 10, pp. 1744-1753, Oct. 2013
  11. Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu, “LineDiff Entropy: lossless layout data compression scheme for maskless lithography systems,” IEEE Signal Processing Letters, Vol. 20, No. 7, pp. 645-648, Jul. 2013
  12. Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang, “Thermal modeling and analysis for 3D-ICs with integrated microchannel cooling,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 9, pp. 1293-1306, Sept. 2011
  13. Philip C. W. Ng, Sheng-Wei Chien, Bo-Sen Chang, Kuen-Yu Tsai, Yi-Chang Lu, Jia-Han Li, Alek C. Chen, “Impact of process-effect correction strategies on variability of critical dimension and electrical characteristics in extreme ultraviolet lithography,” Japanese Journal of Applied Physics, Vol. 50, No. 6, pp. 06GB07:1-9, Jun. 2011
  14. Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Jacky Hong, Chun-Huang Yu, Argy Cheng, Jonathan Chou, Chuan-Jen Chang, Joseph Ku, Tzong-Lin Wu, Ruey-Beei Wu, “Signal/power integrity modeling of high-speed memory modules using chip-package-board co-analysis,” IEEE Trans. Electromagnetic Compatibility, Vol. 52, No. 2, pp. 381-391, May 2010
  15. Tze Wee Chen, Jung Hoon Chun, Yi-Chang Lu, Reza Navid, Wei Wang, Chang-Lee Chen, Robert W. Dutton, “Thermal modeling and device noise properties of 3D-SOI technology,” IEEE Trans. Electron Devices, Vol. 54, No. 4, pp. 656-664, Apr. 2009
  16. Cosmin Iorga, Yi-Chang Lu, Robert W. Dutton, “A built-in technique for measuring substrate and power supply digital switching noise using PMOS-based differential sensors and a waveform sampler in system-on-chip applications,” IEEE Trans. Instrumentation and Measurement, Vol.56, No. 6, pp. 2330-2337, Dec. 2007
  17. Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong, “Performance benefits of monolithically stacked 3-D FPGA,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 216-229, Feb. 2007

Conference & proceeding papers:

  1. Cheng-Yeh Liou, Cheng-Yen Chuang, Chia-Han Huang, Yi-Chang Lu, “HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain,” 2020 IEEE International Conference on Visual Communications and Image Processing (VCIP), 1~4, Macau, China, Dec. 2020
  2. Chun-Hsien Ho, Yi-Hsien Lin, Jennifer Shueh-Inn Hu, Yi-Chang Lu, “Design and Implementation of a Hand-held Lensless Light Field Camera,” 2020 IEEE International Conference on Consumer Electronics - Asia (ICCE-Asia), 1~4, Seoul, Korea (South), Nov. 2020
  3. Chia-Han Huang, Yi-Chang Lu, “An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1~5, Seville, Spain, Oct. 2020
  4. Yu-Cheng Li, Mao-Jan Lin, Xiao-Xuan Huang, Chien-Yu Chen, Yi-Chang Lu, “Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions,” 2020 IEEE 20th International Conference on Bioinformatics and Bioengineering (BIBE), 23~28, Cincinnati, OH, USA, Oct. 2020
  5. Chi-Yun Yang, Yang-Ming Yeh, Yi-Chang Lu, “Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data,” 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1~3, Hsinchu, Taiwan, Aug. 2020
  6. Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu, “Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks,” 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1~4, Nara, Japan, Oct. 2019
  7. Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu, “Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design,” 2019 IEEE 19th International Conference on Bioinformatics and Bioengineering (BIBE), 563~566, Athens, Greece, Oct. 2019
  8. Yang-Yao Lin, Yi-Hsien Lin, Mao-Jan Lin, Yang-Ming Yeh, Yi-Chang Lu, “A Depth-Assisted Deblurring Flow Using Dual Cameras with Different Exposure Times,” 2019 IEEE International Conference on Consumer Electronics - Asia (ICCE-Asia), 9~10, Bangkok, Thailand, Jun. 2019
  9. Yang-Ming Yeh, Jennifer Shueh-Inn Hu, Yen-Yu Lin, Yi-Chang Lu, “Compressing DNN Parameters for Model Loading Time Reduction,” 2019 IEEE International Conference on Consumer Electronics - Asia (ICCE-Asia), 78~79, Bangkok, Thailand, Jun. 2019
  10. Man-Rong Chen, Hao-Wei Liu, Yi-Hsien Lin, Yi-Chang Lu, “A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1~5, Sapporo, Japan, May 2019
  11. Ching-Fan Chiang, Yang-Ming Yeh, Chi-Yun Yang, Yi-Chang Lu, “Colorization of High-Frame-Rate Monochrome Videos Using Synchronized Low-Frame-Rate Color Data,” 2019 IAPR Workshop series on Computational Color Imaging, 276~285, Chiba, Japan, Mar. 2019
  12. Chien-An Wang, Sheng-Jui Huang, Yu-Cheng Li, Yi-Chang Lu, “An FPGA-based liquid association calculator for genome-wide co-expression analysis,” IEEE International Conference on Digital Signal Processing, pp. 1-4, Shanghai. China, Nov. 2018
  13. Shih-Wei Hsieh, Yao-Cheng Yang, Chi-Ming Yeh, Sheng-Jui Huang, Yi-Chang Lu, “Subpixel-level-accurate algorithm for removing double-layered reflections from a single image,” IEEE International Conference on Image Processing, pp. 395-399, Athens, Greece, Oct. 2018
  14. Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu, “Three-dimensional dynamic programming accelerator for multiple sequence alignment,” IEEE Nordic Circuits and Systems Conference, pp. 1-5, Tallinn, Estonia, Oct. 2018
  15. Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu, “Adaptively banded Smith-Waterman algorithm for long reads and its hardware accelerator,” IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 1-9, Milan, Italy, Jul. 2018
  16. Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu, “A hybrid flow for multiple sequence alignment with a BLASTn based pairwise alignment processor,” IEEE International Symposium on Circuits and Systems, pp. 1-5, Florence, Italy, May 2018
  17. Po-Hsiang Hsu, Yang-Ming Yeh, Chi-Ming Yeh, Yi-Chang Lu, “A high dynamic range light field camera and its built-in data processor design,” IEEE International Symposium on Circuits and Systems, pp. 1-5, Florence, Italy, May 2018
  18. Ya-Fang Shih, Yang-Ming Yeh, Yen-Yu Lin, Ming-Fang Weng, Yi-Chang Lu, Yung-Yu Chuang, “Deep co-occurrence feature learning for visual object recognition,” IEEE Conference on Computer Vision and Pattern Recognition, 7302~7311, Honolulu, HI, USA, Jul. 2017
  19. Che-Wei Chang, Min-Hung Chen, Kuan-Chang Chen, Chi-Ming Yeh, Yi-Chang Lu, “Mask design for pinhole-array-based hand-held flight field cameras with applications in depth estimation,” Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 1~4, Jeju, Korea, Dec. 2016
  20. Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Xiao-Xuan Huang, Yi-Chang Lu, “A special processor design for nucleotide basic local alignment search tool with a new banded two-hit method,” IEEE Nordic Circuits and Systems Conference, 1~5, Copenhagen, Denmark, Nov. 2016
  21. Yang-Ming Yeh, Chi-Ming Yeh, Ying-Yu Tseng, Yi-Chang Lu, “An orthogonal matching pursuit processor for sparse-representation-based light field data compression,” IEEE Global Conference on Consumer Electronics, 1~2, Kyoto, Japan, Oct. 2016
  22. Yi-Hsiang Chen, Nae-Chyun Chen, Yu-Hsiang Kao, Yu-Cheng Li, Yi-Chang Lu, “Queue-based segmentation algorithm for refining depth maps in light field camera applications,” IEEE Global Conference on Consumer Electronics, 1~2, Kyoto, Japan, Oct. 2016
  23. Yu-Hsiang Kao, Sheng-Jui Huang, Yi-Chang Lu, “An iterative re-weighted least squares processor design for deblurring parabolic camera images,” IEEE Global Conference on Consumer Electronics, 1~2, Kyoto, Japan, Oct. 2016
  24. Lu Xiao, Xiao-Xuan Huang, Yi-Chang Lu, “Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation,” International SoC Design Conference, 327~328, Jeju, Korea, Oct. 2016
  25. Xiao-Xuan Huang, Chun-Hsien Ho, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu, “Step Shift: a fast image segmentation algorithm and its hardware implementation for next-generation-sequencing fluorescence data,” IEEE Asia Pacific Conference on Circuits and Systems, 202~205, Jeju, Korea, Oct. 2016
  26. Chun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu, “An FPGA-based quality filter for de novo sequence assembly pipeline,” IEEE Asia Pacific Conference on Circuits and Systems, 139~142, Jeju, Korea, Oct. 2016
  27. Nae-Chyun Chen, Tai-Yin Chiu, Yu-Cheng Li, Yu-Chun Chien, Yi-Chang Lu, “Power efficient special processor design for Burrows-Wheeler-transform-based short read sequence alignment,” IEEE International Biomedical Circuits and Systems Conference, 1~4, Atlanta, GA, USA, Oct. 2015
  28. Yi-An Hsu, Chi-Hsuan Cheng, Yi-Chang Lu, Tzong-Lin Wu, “A prediction method of heat generation in the silicon substrate for 3-D ICs,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems, 89~92, San Jose, CA, USA, Oct. 2015
  29. Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu, “Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs,” Conference on Research in Adaptive and Convergent Systems, 430~436, Prague, Czech Republic, Oct. 2015
  30. Min-Hung Chen, Ching-Fan Chiang, Yi-Chang Lu, “Depth estimation for hand-held light field cameras under low light conditions,” International Conference on 3D Imaging, pp. 1-4, Liège, Belgium, Dec. 2014
  31. Che-Wei Chang, Man-Rong Chen, Po-Hsiang Hsu, Yi-Chang Lu, “A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data,” IEEE International Symposium on Circuits and Systems, pp. 786-789, Melbourne, Australia, Jun. 2014
  32. Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James C.-M. Li, Tzong-Lin Wu, Krishnendu Chakrabarty, “Test generation of path delay faults induced by defects in power TSV,” Asian Test Symposium, pp. 43-48, Yilan, Taiwan, Nov. 2013
  33. Ping-Sheng Lin, Yi-Jung Chen, Chai-Lin Yang, Yi-Chang Lu, “Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs,” IEEE International Symposium on Low Power Electronics and Design, pp. 304, Beijing, China, Sept. 2013
  34. Yu-Long Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu, “Architecture and circuit design of parallel processing elements for de novo sequence assembly,” IEEE International System-on-Chip Conference, pp. 50-54, Erlangen, Germany, Sept. 2013
  35. Shih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu, “Light field data processor design for depth estimation using confidence-assisted disparities,” IEEE International System-on-Chip Conference, pp. 129-133, Erlangen, Germany, Sept. 2013
  36. Chun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu, “Analysis and implementation of discrete wavelet transformation for compressing four-dimensional light field data,” IEEE International System-on-Chip Conference, pp. 134-138, Erlangen, Germany, Sept. 2013
  37. Chin-Khai Tang and Yi-Chang Lu, “A power-efficient asynchronous circuit style with selective-channel restoring,” IEEE Midwest Symposium on Circuits and Systems, pp. 25-28, Columbus, OH, USA, Aug. 2013
  38. Yuan-Hsiang Kuo, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu, “Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly,” IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 1158-1161, Vancouver, Canada, May 2013
  39. Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang, “Thermal coupling aware task migration using neighboring core search for many-core systems,” International Symposium on VLSI Design, Automation and Test, pp.42-45, Hsin-Chu, Taiwan, Apr. 2013
  40. Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu, “Power distribution network modeling for 3D ICs with TSV arrays,” Asia and South Pacific Design Automation Conference, pp. 17-22, Yokohama, Japan, Jan. 2013
  41. Ying-Cheng Tseng, Chang-Bao Chang, Chin-Khai Tang, Chih-Hsuan Cheng, Yi-Chang Lu, Kun-You Lin, Tzong-Lin Wu, Ruey-Beei Wu, “Design considerations for radio frequency 3DICs,” IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 197-200, Taipei, Taiwan, Dec. 2012
  42. Cheng-Hong Lin, Yi-Chang Lu, Chin-Khai Tang, Kuen-Yu Tsai, “The effects of NBTI on 3D integrated circuits,” IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 201-204, Taipei, Taiwan, Dec. 2012
  43. Yu-Jen Chang, Hao-Hsiang Chuang, Yi-Chang Lu, Yih-Peng Chiou, Tzong-Lin Wu, Peng-Shu Chen, Shih-Hsien Wu, Tzu-Ying Kuo, Chau-Jie Zhan, Wei-Chung Lo, “Novel crosstalk modeling for multiple Through-Silicon-Vias (TSV) on 3-D IC: experimental validation and application on Faraday cage design,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 232-235, Tempe, AZ, USA, Oct. 2012
  44. Yu-Jen Chang, Tai-Yu Zheng, Hao-Hsiang Chuang, Chuen-De Wang, Peng-Shu Chen, Tzu-Ying Kuo, Chau-Jie Zhan, Shih-Hsien Wu, Wei-Chung Lo, Yi-Chang Lu, Yih-Peng Chiou, Tzong-Lin Wu, “Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC Interposer,” IEEE 62nd Electronic Components and Technology Conference, pp. 1934-1938, San Diego, CA, USA, May 2012
  45. Yong-Ruei Huang, Chia-Hung Pan, Yi-Chang Lu, “Thermal-aware router-sharing architecture for 3D Network-on-Chip design,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 1087-1090, Kuala Lumpur, Malaysia, Dec. 2010
  46. Chih-Chieh Chen, Shih-Chieh Fan Chiang, Xiao-Xuan Huang, Ming-Shing Su, Yi-Chang Lu, “Depth estimation of light field data from pinhole-masked DSLR cameras,” IEEE International Conference on Image Processing, pp. 1769-1772, Hong Kong, China, Sept. 2010
  47. Ming-Shing Su, Kuen-Yu Tsai, Yi-Chang Lu, Yu-Hsuan Kuo, Ting-Hang Pei, Jia-Yu Yen, “Architecture for next-generation massively parallel maskless lithography system,” SPIE Advanced Lithography, San Jose, CA, USA, Mar. 2010
  48. Chih-Chieh Chen, Yi-Chang Lu, Ming-Shing Su, “Light field based digital refocusing using a DSLR camera with a pinhole array mask,” IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 751-754, Dallas, TX, USA, Mar. 2010
  49. Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu, “A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects,” Asia and South Pacific Design Automation Conference, pp. 651-656, Taipei, Taiwan, Jan. 2010
  50. Hitoshi Mizunuma, Chia-Ling Yang, Yi-Chang Lu, “Thermal modeling for 3D-ICs with integrated microchannel cooling,” IEEE/ACM International Conference on Computer-Aided Design, pp. 256-263, San Jose, CA, USA, Nov. 2009
  51. Sheng-Yao Chen, Chin-Khai Tang, Yi-Chang Lu, “An MSB-first 1-of-N single-track asynchronous add-compare-select unit for Viterbi decoders,” International Conference on Communication, Circuits, and Systems, pp. 361-364, San Jose, CA, USA, Jul. 2009
  52. Yi-Chang Lu, “3D technology based circuit and system design,” International Conference on Communications, Circuits, and Systems, pp. 1124-1128, San Jose, CA, USA, Jul. 2009
  53. Yu-Hsiang Lin, Jonathan Chou, Yi-Chang Lu, Tzong-Lin Wu, Hsin-Shu Chen, “Chip-package-board co-design – a DDR3 system design example from circuit designers’ perspective,” IEEE Symposium on Electrical Design of Advanced Packaging and Systems, pp. 27-30, Seoul, Korea, Dec. 2008
  54. Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng, “A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithograpgy effects,” IEEE/ACM International Conference on Computer-Aided Design, pp. 286-291, San Jose, CA, USA, Nov. 2008
  55. Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu, “An asynchronous circuit design with fast forwarding technique at advanced technology node,” IEEE International Symposium on Quality Electronic Design, pp. 769-773, San Jose, CA, USA, Mar. 2008
  56. Tzw Wee Chen, Jung Hoon Chun, Yi-Chang Lu, Reza Navid, Wei Wang, Robert W. Dutton, “Thermal modeling and device noise properties of 3D-SOI technology,” IEEE International SOI Conference, pp. 89-90, Indian Wells, CA, USA, Oct. 2007
  57. Meng-Fu You, Philip C.W. Ng, Yi-Sheng Su, Kuen-Yu Tsai, Yi-Chang Lu, “Impacts of optical proximity correction settings on electrical performance,” SPIE on Advanced Lithography, Vol. 6521, San Jose, CA, USA, Mar. 2007
  58. Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong, “Performance benefits of monolithically stacked 3D-FPGA,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 113-122, Monterey, CA, USA, Feb. 2006
  59. Jae Wook Kim, Yi-Chang Lu, Robert W. Dutton, “Modeling and simulation of jitter in phase-locked loops due to substrate noise,” IEEE International Behavioral Modeling and Simulation Conference, pp. 25-30, San Jose, CA, USA, Sept. 2005
  60. Yi-Chang Lu, Jae Wook Kim, Nobuhiko Nakano, Dave Colleran, Patrick Yue, Robert W. Dutton, “Realization of digital noise emulator for characterization of systems exposed to substrate noise,” Synthesis and Signal Integration of Mixed Information Technologies, pp. 196-203, Hiroshima, Japan, Oct. 2004
  61. Georgios Veronis, Yi-Chang Lu, Robert W. Dutton, “Modeling of wave behavior of substrate noise coupling for mixed-signal IC design,” IEEE International Symposium on Quality Electronic Design, pp. 303-308, San Jose, CA, USA, Apr. 2004
  62. Hai Lan, Yi-Chang Lu, Nobuhiko Nakano, Robert W. Dutton, “Efficient techniques for reducing complexity of substrate models in mixed-signal ICs,” Synthesis and Signal Integration of Mixed Information Technologies, pp. 83-88, Kyoto, Japan, Apr. 2003
  63. Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi, “Min/max on-chip inductance models and delay metrics,” IEEE/ACM Design Automation Conference, pp. 341-346, Las Vegas, NV, USA, Jun. 2001
  64. Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton, “A fast analytical technique for estimating the bounds of on-chip clock wire inductance,” IEEE Custom Integrated Circuits Conference, pp. 241-244, San Diego, CA, USA, May 2001

Patents:

  1. Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, “Determining proximity effect parameters for non-rectangular semiconductor structures,” US Patent, No. 10,007,752, Jun. 2018
  2. Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, “Determining proximity effect parameters for non-rectangular semiconductor structures,” US Patent, No. 9,087,173, Jul. 2015
  3. 郭宇軒、蘇明信、盧奕璋、蔡坤諭, “電子束曝光裝置、電子束產生裝置及曝光方法,” 中華民國專利,I410757, Oct. 2013
  4. 盧奕璋、李政鴻、郭仲宇、吳宗佑, “參考電壓/電流產生系統之佈局,” 中華民國專利,I410185, Sept. 2013
  5. 盧奕璋、李政鴻、郭仲宇、吳宗佑, “電源分佈系統,” 中華民國專利,I375490, Oct. 2012
  6. Yi-Chang Lu, Cheng-Hung Li, Chung-Yui Kuo, and Tsung-Yu Wu, “Layout of a reference generating system,” US Patent, No. 8,148,971, Apr. 2012
  7. Yi-Chang Lu, cheng-Hung Li, Chung-Yui Kuo, Tsing-Yu Wu, “Power distribution system,” US Patent, No. 7,952,229, May 2011

other:

  1. Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu, “A memory-efficient FM-index constructor for next-generation sequencing applications on FPGAs,” Feb. 2021, arXiv preprint arXiv:2102.03045
  2. Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu, “Opportunities of synergistically adjusting voltage-frequency levels of cores and DRAMs in CMPs with 3d-stacked DRAMs for efficient thermal control,” Mar. 2016, ACM SIGAPP Applied Computing Review
  3. Yi-Chang Lu, “Digital noise emulator for characterization of phase-locked-loop systems exposed to substrate noise,” Jan. 2005, Ph.D. Dissertation