With the high-speed trend of the electronic circuits and the widely spreading of the wireless communications, the electromagnetic compatibility (EMC) issue resulted from the electromagnetic radiation and interfernce between the digital and/or RF circuits becomes one of the main challenges for the system-on-chip (SOC) and system-on-package (SOP) designs. The EMC Group dedicates on the analysis, design, and measurement for the EMC problems in the high-speed/high-frequency circuits from either chip-level or package-level points of view. Our research includes
1. Power Integrity and their EMC design: This topic focuses on modeling and measurement for the simulatneous switching noise (SSN) or the power/ground bounce noise (P/GBN) in the high-speed digital circuits from chip, package, and PCB level. The electromagnetic interfernce (EMI) issue casued by these noise is also studied. Several novel solutions to eliminate the noises are investigated.
2. Signal Integrity: This topic focuses on the developement of the time-domain algorithm for extracting the SPICE equivalent models of the high-speed/high-frequency interconnects. Analysis and measurement of the signal quality for the interconnects are also studied.
3. Shielding Effectiveness (SE): This topic fosuses on the design, modeling, and measurement of the SE of the composite material applied in the high-speed optical/electronic package housing.
4. System-level Electro-static Discharge (ESD): This topic focuses on the modeling and measurement techniques for the ESD phenomena in the electronic circuits. Solutions for the ESD issues are also studied.