李致毅 Jri Lee
國立臺灣大學電機工程學系 教授
Professor, Department of Electrical Engineering, National Taiwan University
主要研究領域:
超寬頻無線收發器、光纖通訊電路、鎖相迴路、資料轉換器。Major Research Areas:
Ultrawide Band (UWB) Transceivers, Optical Communication Circuits, Phase-Locked Loops, and Data Converers.研究領域摘要:
李致毅博士的研究興趣包括寬頻通訊電路，超寬頻無線收發器，鎖相迴路與低雜訊寬頻放大電路，高速類比/數位轉換器，及深次微米下主被動元件之模型。
Research Summary:
Dr. Lee's research interests include broadband data communication circuits, wireless transceivers, phase-locked loops and low-noise broadband amplification, A/D and D/A converters, and modeling of passive and active devices in deep-submicron CMOS technologies.
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B.S.
National Taiwan University, 1995 -
M.S.
UCLA, 2003 -
Ph.D.
UCLA, 2003
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Address
EE2-309,
Department of Electrical Engineering,
National Taiwan University,
Taipei 106, Taiwan -
Phone
+886-2-33663583 -
FAX
+886-2-2368-1679 -
Email:
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Personal Homepage
http://cc.ee.ntu.edu.tw/~jrilee/
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Lab. Homepage:
代表性著作 Selected Publication
- Jri Lee, M. Liu, and H. Wang, “A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 1414-1426, Jun. 2008
- Jri Lee, “A 75GHz PLL in 90nmCMOS,” nternational Solid-State Circuits Conference, pp. 432-433, San Francisco, Feb. 2007
- Jri Lee, Jian-yu Ding, Tuan-yi Cheng, “A 20-Gb/s 2-to-1MUX and a 40-GHz VCO in 0.18-um CMOS Technology,” Symposium on VLSI Circuits, Tyoto, Japan, Jun. 2005
- Jri Lee and Shanghann Wu, “Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-um CMOS Technology,” Symposium on VLSI Circuits, Tyoto, Japan, Jun. 2005
- SriKanth Gondi, Jri Lee and Behzad Razavi,, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications,” International Solid-State Circuits Conference, pp. 328-329, San Francisco, Feb. 2005
- Jri Lee and Da-wei Chiu, “A 7-Band 3-8 GHz Frequency Synthesizer with 1-ns Band-Switching Time in 0.18-um CMOS Technology,” International Solid-State Circuits Conference, pp. 204-205, San Francisco, Feb. 2005
- Jri Lee, Ken Kundert and Behzad Razavi, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1571-1580, Sept. 2004
- Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-um CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004
- Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2181-2190, Dec. 2003
- Jri Lee, Ken Kundert and Behzad Razavi, “Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits,” Custom Integrated Circuits Conference, pp. 711-714, San Jose, Sept. 2003
- Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-um CMOS Technology,” Symposium on VLSI Circuits, pp. 259-262, Tyoto, Japan, Jun. 2003
- Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology,” International Solid-State Circuits Conference, pp. 242-243, San Francisco, Feb. 2003