Our Lab's research areas would include low-power, high-speed, high-precision Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) for wire/wireless communications, analog-frond-end (AFE) circuit for IoT sensor, 60GHz/77GHz/84GHz transceiver and wideband high-speed high-end measurement equipment system, Energy-Harvesting Power IC Design, low-jitter Phase-Locked Loop (PLL)/Delay-Locked Loop (DLL) clock generation in mixed-signal systems, and practical aspects of analog/mixed-signal Integrated Circuit (IC) design for System-On-Chip (SOC). The A/D Converter architectures will include SAR, pipeline, subranging, flash, and time-interleave. The D/A Converters will focus on the current-steering segmented architecture. The AC-DC and DC-DC Converters would achieve high efficiency and low transient ripple. The research interest on the low-jitter PLL/DLL would emphasize on its usage to avoid the clock skew in a high-speed, high-precision sampled-data system such as an ADC system. The design of high-speed I/O circuit would combine with signal and power integrity considerations to produce high-speed, low-voltage interface circuitry. In general, the research focuses on low-power high-speed mixed-signal IC design.