胡璧合副教授的著作列表 - Publication List of Vita Pi-Ho Hu

Publication List of 胡璧合 Vita Pi-Ho Hu

Journal articles & book chapters:

  1. V. P.-H. Hu, C.-W. Su, Y.-W. Lee, T.-Y. Ho, C.-C. Cheng, T.-C. Chen, T. Y.-T. Hung, J.-F. Li, Y.-G. Chen, and L.-J. Li, “Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2 FETs for SoC Scaling,” IEEE Transactions on Electron Devices, vol. 67, no. 10, 4216~4221, Oct. 2020
  2. V. P.-H. Hu, H.-H. Lin, Y.-K. Lin, and C. Hu, “Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET),” IEEE Transactions on Electron Devices, 67, 2593~2599, Jun. 2020
  3. M. Gupta and V. P.-H. Hu, “Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications,” IEEE Electron Device Letters, 41, 473~476, Mar. 2020
  4. V. P.-H. Hu, P.-C. Chiu, and Y.-C. Lu, “Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs,” IEEE Journal of the Electron Devices Society, 7, 295~302, 2019
  5. V. P.-H. Hu and C.-T. Wang, “Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression,” Japanese Journal of Applied Physics, 57, 04FD18~undefined, Mar. 2018
  6. V. P.-H. Hu and P.-C. Chiu, “Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs,” Japanese Journal of Applied Physics, 57, 04FD02~undefined, Feb. 2018
  7. V. P.-H. Hu, “Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier,” IEEE Journal of the Electron Devices Society, 5, 107~111, Mar. 2017
  8. C.-H. Yu, M.-L. Fan, K.-C. Yu, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications,” IEEE Transactions on Electron Devices, 63, 625~630, Feb. 2016
  9. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist,” IEEE Transactions on Electron Devices, 62, 1710~1715, Jun. 2015
  10. C.-W. Hsu, M.-L. Fan, V. P.-H. Hu, and Pin Su, “Investigation and Simulation of Work-Function Variation for III–V Broken-Gap Heterojunction Tunnel FET,” IEEE Journal of the Electron Devices Society, 3, 194~199, May 2015
  11. Y.-N. Chen, C.-J. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits,” Journal of Low Power Electronics and Applications, 5, 101~115, May 2015
  12. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, C.-W. Hsu, Pin Su and C.-T. Chuang, “Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET,” IEEE Transactions on Electron Devices, 62, 107~113, Jan. 2015
  13. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 4, 389~399, Dec. 2014
  14. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices,” IEEE Transactions on Circuits and Systems I: Regular Papers, 61, 3339~3347, Dec. 2014
  15. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling,” IEEE Transactions on Electron Devices, 61, 3448~3455, Oct. 2014
  16. M.-L. Fan, S.-Y. Yang, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits,” Microelectronics Reliability, 54, 698~711, Apr. 2014
  17. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET,” IEEE Transactions on Electron Devices, 60, 3596~3600, Oct. 2013
  18. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation,” IEEE Transactions on Nanotechnology, 12, 524~531, Jul. 2013
  19. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET,” IEEE Transactions on Electron Devices, 60, 2038~2044, Jun. 2013
  20. Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su and C.-T. Chuang, “Design and Analysis of Robust Tunneling FET SRAM,” IEEE Transactions on Electron Devices, 60, 1092~1098, Mar. 2013
  21. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells,” IEEE Transactions on Electron Devices, 60, 147~152, Jan. 2013
  22. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, 59, 878~882, Dec. 2012
  23. M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits,” IEEE Transactions on Electron Devices, 59, 2227~2234, Aug. 2012
  24. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, “Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs,” IEEE Transactions on Electron Devices, 59, 1851~1855, Jul. 2012
  25. C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, “Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20, 1201~1210, Jul. 2012
  26. C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, “Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs,” IEEE Transactions on Nanotechnology, 11, 287~291, Mar. 2012
  27. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking,” IEEE Electron Device Letters, 33, 197~199, Feb. 2012
  28. V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1, 335~342, Sept. 2011
  29. V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, P. Su and C.-T. Chuang, “FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics,” IEEE Transactions on Electron Devices, 58, 805~811, Mar. 2011
  30. V. P.-H. Hu, Y.-S. Wu, and P. Su, “Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET,” IEEE Transactions on Nanotechnology, 10, 325~330, Mar. 2011
  31. V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, P. Su and C.-T. Chuang, “Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's Equation,” IEEE Transactions on Electron Devices, 56, 2120~2127, Sept. 2009

Conference & proceeding papers:

  1. C. J. Su, M. K. Huang, K. S. Lee, V. P.-H. Hu et al., “3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T 1R Configuration Demonstrated on Full Wafer,” International Electron Devices Meeting (IEDM), Dec. 2020
  2. V. P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, T.-Y. Ho, Y.-W. Lee, C.-W. Su, and C.-J. Su, “Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications,” 2019 Symposium on VLSI Technology, Kyoto, Japan
  3. V. P.-H. Hu, P.-C. Chiu, A. B. Sachid, and C. Hu, “Negative capacitance enables FinFET and FDSOI scaling to 2 nm node,” 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA
  4. Z.-A. Zheng and V. P.-H. Hu, “Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan
  5. H.-H. Lin and V. P.-H. Hu, “Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET,” 2019 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA
  6. P.-C. Chiu and V. P.-H. Hu, “Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation,” 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe