胡振國特聘教授的著作列表 - Publication List of Jenn-Gwo Hwu

Publication List of 胡振國 Jenn-Gwo Hwu

Journal articles & book chapters:

  1. H.J.Li, C.F.Yang and J.G.Hwu*, “Two Capacitance States Memory Characteristic in Metal-oxide-semiconductor (MOS) Structure Controlled by An Outer MOS Gate Ring,” IEEE Transactions on Electron Devices, Vol. 66, No.3, 1249~1254, Mar. 2019
  2. C.F.Yang, P.J.Chen, W.C.Chen, K.W.Lin, and J.G.Hwu*, “Gate Oxide Local Thinning Mechanism Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor,” IEEE Transactions on Electron Devices, Vol.61, No.1, 279~285, Jan. 2019
  3. W.C.Chen, C.F.Yang and J.G.Hwu*, “Enhanced Two States Current in MOS-Gated MIS Separate Write/Read Storage Device by Oxide Soft Breakdown in Remote Gate,” IEEE Transactions on Nanotechnology, Vol.18, No.1, 62~67, Jan. 2019
  4. Y.H.Chen and J.G.Hwu, “Light Sensing Enhancement and Energy Saving Improvement in Concentric Double MIS(p) Tunnel Diode Structure with Inner Gate Outer Sensor (IGOS) Operation,” IEEE Transactions on Electron Devices, Vol.65, No.11, 4910~4915, Nov. 2018
  5. P.K.Chang and J.G.Hwu*, “Enhanced irradiance sensitivity of 4H-SiC based ultraviolet sensor introducing laterally gated Al/SiO2/SiC tunnel diode structure with low gate bias,” Journal of Applied Physics,, Vol.124, No.2, 024503-1~024503-6, Jul. 2018
  6. C.T.Lin and J.G.Hwu*, “Improved C-V Hysteresis &Two-States Characteristics in MIS (p) Structure with Elongated Thin Metal Gate,” Electrochemical Society Transactions, Vol. 85, No.6, 51~47, May 2018
  7. C.H.Chan and J.G.Hwu*, “On/off Current Ratio Enhancement by Reducing Electrode Separation in Gate-Controlled MIS Tunnel Transistor,” Electrochemical Society Transactions, Vol. 85, No.8, 65~71, May 2018
  8. H.Y.Chen and J.G.Hwu*, “Photo Sensitivity Enhanced by the Modulation of Oxide Thickness in MIS(p) Structure,” Electrochemical Society Transactions, Vo. 85, No. 13, 1441~1448, May 2018
  9. C.F.Yang and J.G.Hwu*, “Light-to-Dark Current Ratio Enhancement on MIS Tunnel Diode Ambient Light Sensor by Oxide Local Thinning Mechanism and Near Power-Free Neighboring Gate,” IEEE Transactions on Electron Devices, Vol.65, No.5,, 1810~1816, May 2018
  10. P.K.Chang and J.G.Hwu*, “Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric,” Applied Physics A, Vol. 124, No.2, 87-1~87-7, Feb. 2018
  11. C.F.Yang and J.G.Hwu*, “Tunable Negative Differential Resistance in MISIM Tunnel Diodes Structure with Concentric Circular Electrodes Controlled by Designed Substrate Bias,” IEEE Transactions on Electron Devices, Vol. 64, No.12, December, PP.5230-5235., 5230~5235, Dec. 2017
  12. K.H.Tseng, C.S.Liao, and J.G.Hwu*, “Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness,” IEEE Transactions on Nanotechnology, Vol. 16, No.6, 1011~1015, Nov. 2017
  13. T.H.Lee, C.S.Liao, and J.G.Hwu*, “Modulation of Minority Carriers in the C-V Characteristics of MIS Tunneling Diode by Surrounding MOS Capacitor,” Electrochemical Society Transactions, Vol.80, No.1, 387~392, Oct. 2017
  14. C.F.Yang and J.G.Hwu*, “Double Negative Differential Resistance Properties in MISIM Structure with Substrate Grounded and Two Electrode Terminals Biased with Constant Offset Voltage,” Electrochemical Society Transactions, Vol.80, No.1, 81~89, Oct. 2017
  15. M.H.Yang and J.G.Hwu*, “MIS(p) Saturation Tunneling Current Controlled By Neighboring MIS Inversion Level Via Coupling Effec,” Electrochemical Society Transactions, Vol.77, No.5, 81~92, May 2017
  16. C.J.Chou and J.G.Hwu*, “Rearrangement of Fringing Field by Sidewall Passivated Metal Gate in MIS Tunnel Diode,” Electrochemical Society Transactions, Vol.77, No.5, 99~107, May 2017
  17. W.T.Hou, W.C.Kao, and J.G.Hwu*, “Enhancement of Light-to-Dark Current Ratio via Coupling Effect for MIS (p) Tunnel Diode Photo Sensors,” Electrochemical Society Transactions, Vol.77, No.5, 249~258, May 2017
  18. M.H.Yang and J.G.Hwu*, “Influence of neighboring coupling on metal-insulator-semiconductor (MIS) deep-depletion tunneling current via Schottky barrier height modulation mechanism,” Journal of Applied Physics, Vol.121,, 154504-1~154504-6, Apr. 2017
  19. P.K.Chang and J.G.Hwu*, “Investigation of interface property in Al/SiO2/n-SiC structure with thin gate oxide by illumination,” Applied Physics A, Vol.123, 261-1~261-8, Mar. 2017
  20. P.K.Chang and J.G.Hwu*, “Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric,” Applied Physics A, Vol. 124, No.2, 87-1~87-7, Feb. 2017
  21. C.F,Yang and J.G.Hwu*, “Role of Fringing Field on The Electrical Characteristics of Metal-Oxide- Semiconductor Capacitors with Co-Planar and Edge-Removed Oxides,” AIP Advances, Vol.6, 125017-1~125017-7, Dec. 2016
  22. C.S.Liao, W.C.Kao, and J.G.Hwu*, “Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading with an MIS Tunnel Diode Sensor,” IEEE Journal of the Electron Devices Society, Vol.4, No.6, 424~429, Nov. 2016
  23. C.S.Liao and J.G.Hwu*, “Current Coupling Effect in MIS Tunnel Diode with Coupled Open-Gated MIS Structure,” Electrochemical Society Transactions, Vol. 75, No.5, 77~86, Oct. 2016
  24. H.H.Lin and J.G.Hwu*, “Local Thinning Induced Less Oxide Breakdown in MOS Structures Due to Lateral Non-Uniformity Effec,” Electrochemical Society Transactions,, Vol. 75, No.5, 63~67, Oct. 2016
  25. W.C.Kao, J.Y.Chen, and J.G.Hwu*, “Transconductance Sensitivity Enhancement in Gated-MIS(p) Tunnel Diode by Self-Protective Effective Local Thinning Mechanism,” Applied Physics Letters, Vol. 109, 063503-1~063503-4, Aug. 2016
  26. H.H.Lin and J.G.Hwu*, “Surface Non-Uniformity Induced Frequency Dispersion in Accumulation Capacitance for Silicon MOS(n) Capacitor,” IEEE Transactions on Electron Devices, Vol.63, No.7, 2844~2851, Jul. 2016
  27. C.S.Liao and J.G.Hwu*, “Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,” IEEE Transactions on Electron Devices, Vol.63, No.7, 2864~2870, Jul. 2016
  28. W.C.Kao, J.Y.Chen, and J.G,Hwu*, “Two States Phenomenon Induced by Neighboring Device Coupling Effect in MIS(p) Tunnel Current,” Electrochemical Society Transactions - Dielectrics for Nanosystems 7: Materials Science, Processing, Reliability, and Manufactur, Vol.72, No.2, 223~230, May 2016
  29. J.Y.Chen, W.C.Kao, and J.G.Hwu*, “Lateral Non-uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide,” Electrochemical Society Transactions - Dielectrics for Nanosystems 7: Materials Science, Processing, Reliability, and Manufactur, Vol.72, No.2, 97~107, May 2016
  30. Y.K.Lin, H.H.Lin, and J.G.Hwu*, “Characterization of Ambient Light Induced Inversion Current in MOS(n) Tunneling Diode with Enhanced Oxide Thickness Dependent Performance,” IEEE Transactions on Electron Devices, Vol.63, No.1, PP.384-389, Jan. 2016
  31. J.Y.Chen, W.C.Kao, and J.G.Hwu, “Enhanced Saturation Current Sensitivities to Charge Trapping and Illumination in MOS Tunnel Diode by Inserting Metal in Gate Dielectric,” Applied Physics A, Vol.122, No.6, June, PP.562-1~562-7., 562-1~562-7, Jan. 2016
  32. Y.D.Tan and J.G.Hwu, “2-State Current Characteristics of MOSCAP with Ultrathin Oxide and Metal Gate,” ECS Solid State Letters, Dielectric Science and Materials (SSS&T), Vol.4, No.12, PP. N23-N25, Dec. 2015
  33. C.S.Liao and J.G.Hwu, “Negative Gate Transconductance in MIS Tunnel Diode Induced By Peripheral Minority Carrier Control Mechanism,” Electrochemical Society Transactions - Semiconductors, Dielectrics, and Metals for Nanoelectronics, Issue 13, Vol. 69, No.5, Oct, Vol.69, No.5, PP.229-235, Oct. 2015
  34. C.S.Liao and J.G.Hwu, “The Device-Perimeter Dependency in the Transient Current of a Metal-Insulator-Metal-Insulator-Semiconductor Capacitor with Anodic Oxide Films,” Electrochemical Society Transactions - Semiconductors, Metal Oxides, and Composites: Metallization and Electrodeposition of Thin, Vol.69, No.31, PP. 49-55, Oct. 2015
  35. C.F.Yang and J.G.Hwu*, “Tunneling Current Induced Frequency Dispersion in the C-V Behavior of Ultra-Thin Oxide Mos Capacitors,” Electrochemical Society Transactions - Semiconductors, Dielectrics, and Metals for Nanoelectronics, Vol.69, No.5, PP.243-248, Oct. 2015
  36. C.S.Liao and J.G.Hwu*, “Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS gated-MIS Tunnel Transistor,” IEEE Transactions on Electron Devices, Vol.62, No.6, P.2061-2065, Jun. 2015
  37. H.H.Lin and J.G.Hwu*, “Influence of Etching Induced Surface Damage on Device Performance with Consideration of Minority Carriers within Diffusion Length from Depletion Edge,” IEEE Transactions on Electron Devices, Vol.62, No.2, PP.634-640, Feb. 2015
  38. Y.C.Liao and J.G.Hwu*, “Intrinsic I-V and C-V Characteristics of Ultra-thin Oxide MOS (p) and MOS (n) Structures under Deep Depletion,” International Journal of Nanotechnology, Jan. 2015
  39. P.H.Tseng, W.C.Tien, S.C. Pan and J.G.Hwu*, “Formation of Single Crystal Si-Nanowire by Electric Field Self-Redistribution Effect in Anodic Oxidation for Multilayer Array Application,” IEEE Transactions on Nanotechnology, Vol. 13, No.6, PP. 1084-1087, Nov. 2014
  40. Y.K.Lin and J.G.Hwu*, “Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors,” IEEE Transactions on Electron Devices, Vol. 61, No. 10, PP. 3562-3565, Oct. 2014
  41. Y.K.Lin and J.G.Hwu*, “Photo-Sensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,” IEEE Transactions on Electron Devices, Vol. 61, No.9, PP.3217-3222, Sept. 2014
  42. C.S.Peng and J.G.Hwu*, “Improvement in the breakdown endurance of high-k dielectric by utilizing stacking technology and adding sufficient interfacial layer,” Nanoscale Research Letters, Vol.9, No.1, 9:464, PP.1-7, Sept. 2014
  43. T.Y.Chen and J.G.Hwu*, “Effect of Trapped Electrons in Ultra-thin SiO2 on the Two-state Inversion Capacitance at Varied Frequencies of Metal-oxide-semiconductor Capacitor,” Applied Physics A, Vol. 116, No.4, PP. 1971-1977, Aug. 2014
  44. Y.K.Lin, Li Lin, and J.G.Hwu*, “Minority Carriers Induced Schottky Barrier Height Modulation in Current Behavior of Metal-Oxide-Semiconductor Tunneling Diode,” ECS Journal of Solid State Science and Technology, Vol. 3, No.6, PP.Q132-Q135, May 2014
  45. H.W.Lu and J.G.Hwu*, “Roles of Interface and Oxide Trap Density on the Kinked Current Behavior of Al/SiO2/Si(p) Structures with Ultra-thin Oxides,” Applied Physics A, Vol.115, No.3, PP.837-842, May 2014
  46. P.H.Tseng and J.G.Hwu*, “Non-Planar Substrate Metal-Oxide-Semiconductor Photo-Capacitance Detectors with Enhanced Deep Depletion Sensitivity at Convex Corner,” ECS Journal of Solid State Science and Technology, Vol.3, No.6, PP. Q104-Q108, Apr. 2014
  47. P.H.Tseng and J.G.Hwu*, “Convex corner induced capacitance-voltage response from depletion to deep depletion in non-planar substrate metal-oxide-semiconductor capacitors with ultra thin oxide,” Thin Solid Films, Vol.556, PP.317-321, Apr. 2014
  48. C.S.Peng and J.G.Hwu*, “Photo-induced Tunneling Currents in MOS Structures with Various HfO2/SiO2 Stacking Dielectrics,” AIP Advances, Vol.4, No.4, PP.047112-1~047112-10, Apr. 2014
  49. C.C.Lin, P.L.Hsu, L.Lin and J.G.Hwu*, “Investigation on edge fringing effect and oxide thickness dependence of inversion current in MOS tunneling diodes with comb-shaped electrodes,” Journal of Applied Physics, Vol.115, No.12, PP.124109-1~124109-6, Mar. 2014
  50. P.H.Tseng and J.G.Hwu*, “Corner Induced Non-uniform Electric Field Effect on the Electrical Reliability of Metal-Oxide-Semiconductor Devices with Non-planar Substrates,” Solid-State Electronics, Vol.91, PP.100-105., Jan. 2014
  51. T.Y.Chen and J.G.Hwu*, “Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-Thin SiO2 Layer,” ECS Journal of Solid State Science and Technology,, Vol. 3, No. 4, PP.Q37-Q41., Jan. 2014
  52. T.Y.Chen and J.G.Hwu*, “Sensitivity Enhancement of Metal-oxide-semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-thin SiO2 Layer,” Electrochemical Society Transactions,, Vol.58, No.8, PP.79-85., Oct. 2013
  53. H.W.Lu and J.G.Hwu*, “Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region due to Edge Fringing Field Effect,” Electrochemical Society Transactions- Semiconductors, Dielectrics, and Metals for Nanoelectronics 11, Vol.58, No.7, PP.339-344., Oct. 2013
  54. C.W.Lee and J.G.Hwu*, “Quantum-mechanical calculation of carrier distribution in MOS accumulation and strong inversion layers,” AIP Advances, Vol.2, No.10, PP.102123-1~102123-18., Oct. 2013
  55. C.C.Lin and J.G.Hwu*, “Performance enhancement of metal-oxide-semiconductor tunneling temperature sensors with nanoscale oxides by employing ultrathin Al2O3 high-k dielectrics,” Nanoscale, Vol.5, No.17, PP. 8090-8097, Aug. 2013
  56. H.W.Lu and J.G.Hwu*, “Roles of Interface and Oxide Trap Density on the Kinked Current Behavior of Al/SiO2/Si(p) Structures with Ultra-thin Oxides,” Applied Physics A, DOI: 10.1007/s00339-013-7873-2, Aug. 2013
  57. T.Y.Chen, C.S.Pang, and J.G.Hwu*, “Effect of Electrons Trapping/De-trapping at Si-SiO2 Interface on Two-state Current in MOS(p) Structure with Ultra-thin SiO2 by Anodization,” ECS Journal of Solid State Science and Technology, Vol. 2, No.9, Q159-164, Jul. 2013
  58. C.M.Hsu and J.G.Hwu*, “Improvement of electrical performance of HfO2/SiO2/4H-SiC structure with thin SiO2,” ECS Journal of Solid State Science and Technology, Vol. 2, No.8, N3072-N3078., Jul. 2013
  59. C.C.Lin and J.G.Hwu*,, “ Nitric acid compensated aluminum oxide dielectrics with improved negative bias reliability and positive bias temperature response,” Journal of Applied Physics, Vol.113, No.5, PP. 054103-1~054103-8, Feb. 2013
  60. T.Y.Chen, H.W.Lu, and J.G.Hwu*, “Effect of H2O on the Electrical Characteristics of Ultra-thin SiO2 Prepared with and without Vacuum Treatments after Anodization,” Microelectronic Engineering, Vol.104., PP.5-10, Jan. 2013
  61. P.H.Tseng and J.G.Hwu*, “Interface Trap Redistribution and Deep Depletion Behavior in Non-planar MOS with Ultra-thin Oxide Grown by Anodic Oxidation,” Electrochemical Society Transactions-Graphene, Ge/III-V, and Emerging Materials for Post CMOS Applications 5, Vol. 53, No. 1, PP.331-341., 2013
  62. C.M.Hsu and J.G.Hwu*, “Investigation of Carbon interstitials with varied SiO2 thickness in HfO2/SiO2/ 4H-SiC structure,” Applied Physics Letters, Vol.101, No.25., PP.253517-1~253517-4, Dec. 2012
  63. P.H.Tseng and J.G.Hwu*, “Non-planar Substrate Effect on the Interface Trap Capacitance of MOS Structures with Ultra Thin Oxides,” Journal of Applied Physics, Vol.112, No.9., PP. 094502-1~094502-7, Nov. 2012
  64. J.C.Chiang and J.G.Hwu*, “Two-State Trap-Assisted Tunneling Current Characteristics in Al2O3/SiO2/SiC Structures With Ultra-thin Dielectrics,” IEEE Transactions on Nanotechnology, Vol.11, No.5., PP.871-876, Sept. 2012
  65. C.C.Lin and J.G.Hwu*, “Investigation of Nonuniformity Phenomenon in Nanoscale SiO2 and High-k Gate Dielectrics,” Journal of Applied Physics, Vol.112, No.6., PP.064119-1~064119-5, Sept. 2012
  66. J.C.Chiang and J.G.Hwu*, “Detrapping Characteristics of Al2O3/SiO2/4H-SiC Stacked Structure with Two-state Trap-assisted Tunnelling Current Behavior,” Journal of Physics D:Applied Physics, Vol.45, P.345303(6pp), Aug. 2012
  67. T.Y.Chen and J.G.Hwu*, “Two States Phenomenon in the Current Behavior of Metal-Oxide-Semiconductor Capacitor Structure with Ultra-thin SiO2,” Applied Physics Letters, Vol.101, No.7., PP. 073506-1~073506-4, Aug. 2012
  68. C.Y.Yang and J.G.Hwu*, “Photo-Sensitivity Enhancement of HfO2-based MOS Photodiode with Specific Perimeter Dependency due to Edge Fringing Field Effect,” IEEE Sensors Journal, Vol.12, No.6., PP.2313-2319., Jun. 2012
  69. C.M.Hsu and J.G.Hwu*, “SiO2 Thickness Dependency of C-V Dispersion in Stacked Al/HfO2/SiO2/4H-SiC Capacitors,” Electrochemical Society Transactions - Dielectrics for Nanosystems 5: Materials Science, Processing, Reliability, and Manufactur, Vol.45, No.3., PP.209-215, May 2012
  70. J.Y.Cheng and J.G.Hwu*, “Characterization of Edge Fringing Effect on the C-V Responses from Depletion to Deep Depletion of MOS(p) Capacitors with Ultrathin Oxide and High-κ Dielectric,” IEEE Transactions on Electron Devices, Vol.59, No.3., PP.565-572, Mar. 2012
  71. J.C.Chiang and J.G.Hwu*, “Investigation of the Two-State Current Conduction Mechanism in High-k/SiO2 Stacked Dielectric with High Bandgap 4H-SiC Substrate,” Journal of the Electrochemical Society, Vol. 158, No.12., PP.G237-G241, Dec. 2011
  72. K.M.Chen and J.G.Hwu*, “Area dependent deep depletion behavior in the capacitance-voltage characteristics of metal-oxide-semiconductor structures with ultra-thin oxides,” Journal of Applied Physics, Vol.110, No.11., PP.114104-1~114104-4, Dec. 2011
  73. C.C.Lin and J.G.Hwu*, “Electrical Characteristics and Temperature Response of Al2O3 Gate Dielectrics with and without Nitric Acid Compensation,” Electrochemical Society Transactions - Physics and Technology of High-k Materials 9, Volume 41, No. 3., PP.361-371, Sept. 2011
  74. C.C.Lin and J.G.Hwu*, “Comparison of The Reliability of Thin Al2O3 Gate Dielectrics Prepared by In-Situ Oxidation of Sputtered Aluminum in Oxygen Ambient with and without Followed Nitric Acid Compensation,” IEEE Transactions on Device and Materials Reliability, Vol.11, No.2., PP.227-235, Jun. 2011
  75. H.W.Lu, T.Y.Chen, and J.G.Hwu*, “Electrical Characteristics Analysis at Oxide Flat-band Voltage for Al-SiO2-Si Capacitor,” Electrochemical Society Transactions- Silicon Nitride, Silicon Dioxide, and Emerging Dielectrics 11, Volume 35, No. 4., PP.639-650, Apr. 2011
  76. J.C.Chiang and J.G.Hwu*, “Two-State Current Conduction in High-k/SiO2 Stacked Dielectric with High Bandgap 4H-SiC Substrate,” Electrochemical Society Transactions - Wide Bandgap Semiconductor Materials and Devices 12, Volume 35, No. 6., PP.165-171, Apr. 2011
  77. T.Y.Chen, H.W.Lu, and J.G.Hwu*, “Influence of Residual Ions and Gases at Si/SiO2 Interface in Ultra-Thin Gate Oxide,” Electrochemical Society Transactions - Processes at the Semiconductor Solution Interface 4, Volume 35, No. 8., PP.201-210, Apr. 2011
  78. S.J.Chang and J.G.Hwu*, “Comprehensive Study on Negative Capacitance Effect Observed in MOS(n) Capacitors with Ultra-thin Gate Oxides,” IEEE Transactions on Electron Devices, Vol.58, No.3., PP.684-690, Mar. 2011
  79. C.Y.Wang and J.G.Hwu*, “Characterization of Stacked Hafnium Oxide (HfO2) / Silicon Dioxide (SiO2) Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors,” Journal of the Electrochemical Society, Vol.157, No.10., PP. J324-J328., Oct. 2010
  80. J.Y.Cheng, H.T.Lu, and J.G.Hwu*, “Metal-Oxide-Semiconductor Tunneling Photodiodes with Enhanced Deep Depletion at Edge by High-k Material,” Applied Physics Letters, Vol.96, No. 23., PP. 233506-1~233506-3., Jun. 2010
  81. C.H.Chen and J.G.Hwu*, “Stack Engineering of Low-Temperature-Processing Al2O3 Dielectrics Prepared by Nitric Acid Oxidation for MOS Structure,” Microelectronics Engineering, Vol.87, pp. 686-689, Jan. 2010
  82. K.C.Chuang and J.G.Hwu*, “Thin Silicon Oxide Films on N-type 4H-SiC Prepared by Scanning Frequency Anodization Method,” Microelectronics Engineering, Vol.86, No.11, PP. 2207-2210, Nov. 2009
  83. J.Y.Cheng, C.T.Huang, and J.G.Hwu*, “Comprehensive study on the deep depletion capacitance-voltage behavior for metal-oxide-semiconductor capacitor with ultra-thin oxides,” Journal of Applied Physics, Vol.106, No.7, PP.074507-1~074507-7, Oct. 2009
  84. C.Y.Wang and J.G.Hwu*, “Characterization of Stacked Hafnium Oxide (HfO2)/Silicon Dioxide (SiO2) Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors,” Electrochemical Society Transactions - Physics and Technology of High-k Gate Dielectric 7, Volume 25, No.6, PP.361-370, Sept. 2009
  85. J.Y.Cheng, C.T.Huang, and J.G.Hwu*, “Comparison of Lateral Non-uniformity Phenomena between HfO2 and SiO2 from Magnified C-V Curves in Inversion Region,” Electrochemical Society Transactions - Physics and Technology of High-k Gate Dielectric 7, Volume 25, No.6, PP.327-338, Sept. 2009
  86. C.Y.Yang and J.G.Hwu*, “Low Temperature Tandem Aluminum Oxides Prepared by DAC-ANO Compensation in Nitric Acid,” Journal of the Electrochemical Society, Vol.156, No.11,, PP.G184-G189, Sept. 2009
  87. H.L.Chen, C.J. Lee, and J.G.Hwu*, “Effect of Tensile Stress on MOS Capacitors with Ultra-thin Gate Oxide,” International Journal of Electrical Engineering, Vol.16, No.4, PP.283-287, Aug. 2009
  88. C.H.Chang and J.G.Hwu*, “Characteristics and Reliability of Hafnium Oxide Dielectric Stacks with Room Temperature Grown Interfacial Anodic Oxide,” IEEE Transactions on Device and Materials Reliability, Vol. 9, No.2, PP.215-221., Jun. 2009
  89. C.H.Chen, K.C.Chuang and J.G.Hwu*, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors with Ultra-thin Oxides and High-k Dielectrics,” IEEE Transactions on Electron Devices, Vol.56, No.6,, PP.1262-1268, Jun. 2009
  90. C.H.Chang and J.G.Hwu*, “Trapping Characteristics of Al2O3/HfO2/SiO2 Stack Structure Prepared by Low Temperature In-situ Oxidation in dc-sputtering,” Journal of Applied Physics, Vol.105, No.9, PP.094103-1~094103-6, May 2009
  91. C.Y.Wang and J.G.Hwu*, “Metal-Oxide-Semiconductor (MOS) Structure Solar Cell Prepared by Low Temperature (< 400oC) Anodization Technique,” Journal of the Electrochemical Society, Vol.156, No.3, PP. H181-H183., Jan. 2009
  92. C.N.Lin, Y.L.Yang, W.T.Chen, S.C.Lin, K.C.Chuang, and J.G.Hwu*, “Effect of Strain-Temperature Stress on MOS Structure with Ultra-thin Gate Oxide,” Microelectronics Engineering, Vol.85, PP.1915-1919., Sept. 2008
  93. K.C.Chuang and J.G.Hwu*, “Silicon Oxide Gate Dielectric on N-Type 4H-SiC Prepared by Low Thermal Budget Anodization Method,” Journal of the Electrochemical Society,, Vol.155, No.8, PP.G159-G162., Aug. 2008
  94. J.C.Tseng and J.G.Hwu*, “Lateral Non-uniformity Effects of Border Traps on The Characteristics of Metal-Oxide-Semiconductor Field-Effect Transistor Subjected to High-Field Stresses,” IEEE Transactions on Electron Devices, Vol.55, No.6, PP.1366-1372., Jun. 2008
  95. H.P.Lin and J.G.Hwu*, “Shallow Level Trap Formation in SiO2 Induced by High Field and Thermal Stresses,” Journal of Applied Physics, Vol.103, PP.104102-1~104102-5., May 2008
  96. C.C.Wang, T.H.Li, K.C.Chuang and J.G.Hwu*, “Study of Ultra-thin Gate Oxides Prepared by Tensile-Stress Oxidation in Tilted Cathode Anodization System,” Journal of the Electrochemical Society, Vol.155, No.3, PP.G61-G64., Mar. 2008
  97. C.H.Chang and J.G.Hwu*, “Reliability of Low Temperature Processing Hafnium Oxide Gate Dielectrics Prepared by Cost-effective Nitric Acid Oxidation (NAO) Technique,” IEEE Transactions on Device and Materials Reliability, Vol. 7, No.4, PP.611-616., Dec. 2007
  98. H.P.Lin and J.G.Hwu*, “Analysis of Constitution and Characteristics of Lateral Nonuniformity Effects of MOS Devices Using QM-based Terman Method,” IEEE Transactions on Electron Devices, Vol. 54, No.11, PP. 3064-3070, Nov. 2007
  99. J.C.Tseng and J.G.Hwu*, “Oxide Trapped Charges Induced by Electrostatic Discharge (ESD) Impulse Stress,” IEEE Transactions on Electron Devices, Vol.54, No.7, PP.1666~1671, Jul. 2007
  100. Y.L.Yang, C.H.Chang, Y.H.Shih, K.Y.Hsieh, and J.G.Hwu*, “Modeling and Characterization of Hydrogen Induced Charge Loss in Nitride Trapping Memory,” IEEE Transactions on Electron Devices, Vol.54, No.6, PP.1360~1365, Jun. 2007
  101. J.C.Chiang and J.G.Hwu*, “Low Temperature (< 400 ℃) Al2O3 Ultrathin Gate Dielectrics Prepared by Shadow Evaporation of Aluminum Followed by Nitric Acid Oxidation,” Applied Physics Letters, Vol.90, No.10, PP.102902-1~102902-3, Mar. 2007
  102. J.C.Tseng and J.G.Hwu*, “Effects of Electrostatic Discharge (ESD) High-Field Current Impulse on Oxide Breakdown”,” Journal of Applied Physics, Vol.101, No.1, PP. 014103-1~014103-6, Jan. 2007
  103. T.M.Wang, C.H.Chang, and J.G.Hwu*, “Enhancement of Temperature Sensitivity of Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors by Utilizing Hafnium Oxide (HfO2) Film Added on Silicon Dioxide (SiO2),” IEEE Sensors Journal, Vol. 6, No. 6, PP. 1468-1472, Dec. 2006
  104. K.C.Chuang and J.G.Hwu*, “Improvement in Electrical Characteristics of High-k Al2O3 Gate Dielectric by Field-Assisted Nitric Oxidation,” Applied Physics Letters, Vol.89, No.23, PP.232903-1~232903-3, Dec. 2006
  105. T.M.Wang, C.H.Chang, S.J.Chang, and J.G.Hwu*, “Comparison of Saturation Current Characteristics for Ultra-thin Silicon Oxides Grown on N- and P-type Silicon Substrates Simultaneously,” Journal of Vacuum Science and Technology A, Vol. 24, No.6, PP.2049-2053, Nov. 2006
  106. S.W.Huang and J.G.Hwu*, “Lateral Nonuniformity of Effective Oxide Charges in MOS Capacitors with Al2O3 Gate Dielectrics,” IEEE Transactions on Electron Devices, Vol.53, No.7, PP.1608-1614, Jul. 2006
  107. C.W.Tung, Y.L.Yang and J.G.Hwu*, “Impact of Strain-Temperature Stress on Ultrathin Oxide,” IEEE Transactions on Electron Devices, Vol.53, No.7, PP.1736-1737, Jul. 2006
  108. C.H. Chang, T.M. Wang, and J.G. Hwu*, “Quality Improvement and Electrical characteristics of High-k Films after Receiving Direct Superimposed with Alternative Current Anodic Oxidation (DAC-ANO) Compensation,” Electrochemical Society Transactions - Physics and Technology of High-k Gate Dielectric III, Volume 1, Volume 1, Issue 5, PP. 465-475, Jan. 2006
  109. S.W. Huang and J.G. Hwu*, “Indication of Lateral Nonuniformity of Effective Oxide Charges in High-k Gate Dielectrics by Terman’s Method,” Electrochemical Society Transactions - Physics and Technology of High-k Gate Dielectric III, Volume 1, Volume 1, Issue 5, PP.789-796, Jan. 2006
  110. C.J.Hung and J.G.Hwu*, “Enhancement in Ultra-thin Oxide Growth by Thermal Induced Tensile Stress,” IEEE Transactions on Device and Material Reliability, Vol.6, No.1, PP.28-32, Jan. 2006
  111. C.H.Huang* and J.G.Hwu, “The Effect of Photon Illumination in Rapid Thermal Processing on The Characteristics of MOS Structures with Ultra-thin Oxides Examined by Substrate Injection,” Solid-State Electronics, Vol.49, No.10, PP.1599-1603, Oct. 2005
  112. T.M. Wang and J.G. Hwu*, “Temperature-Induced Voltage Drop Rearrangement and Its Effect on Oxide Breakdown in MOS Capacitor Structure,” Journal of Applied Physics, Vol.97, No.4, PP.044504-1~5, Apr. 2005
  113. Y.P.Lin and J.G.Hwu*, “Oxide Thickness Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” Journal of The Electrochemical Society, Vol.151, No.12, PP.G853-G857, Dec. 2004
  114. Y.P. Lin and J.G.Hwu*, “Suboxide Characteristics in Ultrathin Oxides Grown under Novel Oxidation Processes,” Journal of Vacuum Science and Technology A, Vol.22, No.6, PP.2265-2272, Nov. 2004
  115. S.W.Huang and J.G.Hwu*, “Ultra-Thin Aluminum Oxide Gate Dielectric on N-Type 4H-SiC Prepared by Low Thermal Budget Nitric Acid Oxidation,” IEEE Transactions on Electron Devices, Vol.51, No.11, PP.1877-1882, Nov. 2004
  116. Y.L.Yang and J.G.Hwu*, “Quality Improvement of Ultra-Thin Gate Oxide by Using Thermal-Growth Followed by Scanning-Frequency Anodization (SF ANO) Technique,” IEEE Electron Device Letters, Vol.25, No.10, PP.687-689, Oct. 2004
  117. W.J.Liao, Y.L.Yang, S.C.Chuang, and J.G.Hwu*, “Growth-Then-Anodization Technique for Reliable Ultra-Thin Gate Oxides,” Journal of The Electrochemical Society, Vol.151, No.9, PP.G549-G553, Sept. 2004
  118. Y.H.Shih, S.R.Lin, T.M.Wang, and J.G.Hwu*, “High Sensitive and Wide Detecting Range MOS Tunneling Temperature Sensors for On-Chip Temperature Detection,” IEEE Transactions on Electron Devices, Vol.51, No.9, PP.1514-1521, Sept. 2004
  119. C.S.Kuo, J.F.Hsu, S.W.Huang, L.S.Lee, M.J.Tsai, and J.G.Hwu*, “High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film in Nitric Acid Followed by High Temperature Annealing,” IEEE Transactions on Electron Devices, Vol.51, No.6, PP.854-858, Jun. 2004
  120. Y.P.Lin and J.G.Hwu*, “Quality Improvement in LPCVD Silicon Nitrides by Anodic and Rapid Thermal Oxidations,” Electrochemical and Solid-State Letters, Vol.7, No.5, PP.G87-G89, May 2004
  121. Z.H.Chen, S.W.Huang, and J.G.Hwu*, “Electrical Characteristics of Ultra-thin Gate Oxides (<3nm) Prepared by Direct Current Superposed with Alternating-current Anodization,” Solid-State Electronics, Vol.48, PP.23-28, Jan. 2004
  122. Y.P.Lin and J.G.Hwu*, “Using Anodization to Oxidize Ultra-Thin Aluminum Film for High-K Gate Dielectric Application,” Journal of The Electrochemical Society, Vol.150, No.7, PP.G389-394, Jul. 2003
  123. S.W.Huang and J.G.Hwu*, “Electrical Characterization and Process Control of Cost Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing,” IEEE Transactions on Electron Devices, Vol.50, No.7,, PP.1658-1664, Jul. 2003
  124. C.C.Hong and J.G.Hwu*, “Stress Distribution on (100) Si Wafer Mapped by Novel I-V Analysis of MOS Tunneling Diodes,” IEEE Electron Device Letters, Vol.24, No.6, PP.408-410, Jun. 2003
  125. C.C.Hong, W.J.Liao, and J.G.Hwu*, “Thickness-Dependent Stress Effect in P-type Metal-Oxide-Semiconductor Structure Investigated by Substrate Injection Current,” Applied Physics Letters, Vol.82, No.22,, PP.3916-3918, Jun. 2003
  126. C.C. Hong, C.Y.Chang, C.Y.Lee, and J.G.Hwu*, “Thermal Stress at Wafer Contact Points in Rapid Thermal Processing Investigated by Repeated Spike Treatment before Oxidation,” Journal of Applied Physics, Vol.93, No.4, PP.2225-2228, Feb. 2003
  127. C.H.Chen, C.C.Hong, and J.G.Hwu*, “Silicon MOS Solar Cells with Oxide Prepared by Room Temperature Anodization in Hydrofluosilicic Acid (H2SiF6) Solution,” Journal of The Electrochemical Society, Vol.149, No.6, PP.G362-G366, Jun. 2002
  128. J.L.Su, C.C. Hong, and J.G.Hwu*, “Enhanced Thermally-Induced Stress Effect on Ultra-thin Gate Oxide,” Journal of Applied Physics, Vol.91, No.8, PP.5423-5428, Apr. 2002
  129. C.C.Hong, J.L.Chen, and J.G.Hwu*, “Improvement of Oxide Thickness Uniformity by High-Then-Low O2 Pressure Oxidation in Rapid Thermal Processing,” Journal of Vacuum Science and Technology A, Vol.20, No.2, PP.544-548, Mar. 2002
  130. C.C.Hong, Y.R.Yen, J.L.Su, and J.G.Hwu*, “Improvement in Ultra-thin Rapid Thermal Oxide Uniformity by The Control of Gas Flow,” IEEE Transactions on Semiconductor Manufacturing, Vol.15, No.1, PP.102-107, Feb. 2002
  131. J.Y.Yen, C.H.Huang, and J.G. Hwu*, “Effect of Mechanical Stress on the Characteristics of Silicon Thermal Oxides,” Japanese Journal of Applied Physics, Vol.41, Part 1, No.1, PP.81-82, Jan. 2002
  132. C.C.Hong, W.R.Chen, and J.G.Hwu*, “Local Thinning-Induced Oxide Nonuniformity Effect on the Tunneling Current of Ultrathin Gate Oxide,” Japanese Journal of Applied Physics, Vol.41, Part 1, No.1, PP.1-4, Jan. 2002
  133. C.C.Hong, C.Y.Chang, C.Y.Lee, and J.G.Hwu*, “Reduction in Leakage Current of Low-Temperature Thin Gate Oxide by Repeated Spike Oxidation (RSO) Technique,” IEEE Electron Devices Letters, Vol.23, No.1, PP.28-30, Jan. 2002
  134. C.C.Ting, Y.H. Shih, and J.G.Hwu*, “Ultra Low Leakage Characteristics of Ultra-thin Gate Oxides (~3 nm) Prepared by Anodization Followed by High Temperature Annealing,” IEEE Transactions on Electron Devices, Vol.49, No.1, PP.179-181, Jan. 2002
  135. Y.P.Lin and J.G.Hwu*, “Application of Anodization to Reoxidize Silicon Nitride Film,” Japanese Journal of Applied Physics, Vol.40, Part 1, No.12, PP.6788-6791, Dec. 2001
  136. C.C.Hong and J.G.Hwu*, “Degradation in Metal-Oxide-Semiconductor Structure with Ultrathin Gate Oxide due to External Compressive Stress,” Applied Physics Letters, Vol.79, No.23, PP.3797-3799, Dec. 2001
  137. C.H.Huang and J.G.Hwu*, “Breakdown Characteristics of Ultra-thin Gate Oxides (< 4 nm) MOS Structures Subject to Substrate Injection,” Journal of Vacuum Science and Technology B, Vol.19(5), PP.1894-1897, Sept. 2001
  138. C.C.Hong, T.Y.Lee, Y.L.Hsieh, C.C.Liu, Y.K.Feng and J.G.Hwu*, “Improvement in Oxide Thickness Uniformity by Repeated Spike Oxidation (RSO),” IEEE Transactions on Semiconductor Manufacturing, Vol.14, No.3, PP.227-230, Aug. 2001
  139. Y.H.Shih and J.G.Hwu*, “An on-Chip Temperature Sensor by Utilizing an MOS Tunneling Diode,” IEEE Electron Device Letters, Vol.22, No.6, PP.299-301, Jun. 2001
  140. C.H.Huang and J.G.Hwu*, “Anomalous Low-Voltage Tunneling Current Characteristics of Ultra-Thin Gate Oxide ( ~ 2 nm) after High Field Stress,” Journal of Applied Physics, Vol.89, No.10, PP.5497-5501, May 2001
  141. J.Y.Yen and J.G.Hwu*, “Stress Effect on the Kinetics of Silicon Thermal Oxidation,” Journal of Applied Physics, Vol.89, No.5, PP.3027-3032, Mar. 2001
  142. Y.C.Chen, C.Y.Lee, and J.G.Hwu*, “Ultra-thin Gate Oxides Prepared by Alternating Current Anodization of Silicon Followed by Rapid Thermal Anneal,” Solid State Electronics, Vol.45, PP.1531-1536, 2001
  143. J.Y.Yen and J.G.Hwu*, “Enhancement of Silicon Oxidation Rate due to Tensile Mechanical Stress,” Applied Physics Letters, Vol.76, No.14, PP.1834-1835, Apr. 2000
  144. C.H.Huang and J.G.Hwu*, “Enhancement in Soft Breakdown Occurrence Frequency for Ultra-thin Gate Oxides Caused by Photon Effect in Rapid Thermal Post Oxidation Annealing,” Solid-State Electronics, Vol.44, PP.1405-1410, 2000
  145. Y.H.Shih and J.G.Hwu*, “Improvement in the Electrical Properties of Thin Gate Oxides by Chemical Assisted Electron Stressing Followed by Annealing (CAESA),” IEEE Electron Device Letters, Vol.20, No.11, PP.545-547, Nov. 1999
  146. K. C. Lee, H. Y. Chang, H. Chang, J. G. Hwu* and T. S. Wung, “The Effect of Patterned Susceptor on The Thickness Uniformity of Rapid Thermal Oxides,” IEEE Transactions on Semiconductor Manufacturing, Vol.12, No.3, PP.340-344, Aug. 1999
  147. K. L. Yeh, M. J. Jeng and J.G. Hwu*, “Fluorinated Thin Oxides Prepared by Room Temperature Deposition Followed by Furnace Oxidation (LPD/FO),” Solid State Electronics, Vol.43, pp.671-676, 1999
  148. Y.H.Chen and J.G.Hwu*, “Light Sensing Enhancement and Energy Saving Improvement in Concentric Double MIS(p) Tunnel Diode Structure with Inner Gate Outer Sensor (IGOS) Operation,” IEEE Transactions on Electron Devices, Vol.65, No.11, 4910~4915

Conference & proceeding papers:

  1. Y.H.Chen and J.G.Hwu*, “Roles of Inner and Outer Fringe and Asymmetric Coupling Effect in Concentric Double-MIS(p) Tunneling Diodes,” 235th ECS Meeting, G01:1199~1199, Dallas, Texas, USA, May 2019
  2. J.G.Hwu*, C.F.Yang, and C.S.Liao, “Enhancement of Coupling Effect in Concentric Double MIS Tunnel Diodes with Local Oxide Thinning Mechanism,” WCSM 2019, 5th Annual World Congress of Smart Materials, 2019, 75~75, Rome, Italy, Mar. 2019
  3. J.G.Hwu*, C.F.Yang, C.S.Liao, and H.W.Lu, “Negative Transconductance in Coupled MIS(p) Tunnel Diodes with Concentric Gate Structure,” International Electronic Devices and Materials Symposium - IEDMS 2018, W2A: 24~24, National Taiwan Ocean University, Keelung, Taiwan, ROC (Invite, Nov. 2018
  4. Y.H.Liu and J.G.Hwu*, “Origin of the Transient Current Peaks in MIS Structures Observed During I-V Measurement,” International Electronic Devices and Materials Symposium - IEDMS 2018, C-170:162~162, National Taiwan Ocean University, Keelung, Taiwan, ROC, Nov. 2018
  5. J.G.Hwu*, C.F.Yang, and C.S.Liao, “Negative Differential Resistance Behavior in Coupled MIS(p) Tunnel Diodes,” Nano Science & Technology - Nano S&T 201, P.225~P.225, Potsdam, Germany, Oct. 2018
  6. H.Y.Chen and J.G.Hwu*, “Photo Sensitivity Enhanced By the Modulation of Oxide Thickness in MIS (p) Structure,” 233rd ECS Meeting, M01-2464~M01-2464, Seattle, WA, USA, May 2018
  7. C.H.Chan and J.G.Hwu*, “On/Off Current Ratio Enhancement By Reducing Electrode Separation in Gate-Controlled MIS Tunnel Transistor,” 233rd ECS Meeting, H02-1459.~H02-1459., Seattle, WA, USA, May 2018
  8. C.T.Lin and J.G.Hwu*, “Improved C-V Hysteresis and Two-States Characteristics in MIS (p) Structure with Elongated Thin Metal Gate,” 233rd ECS Meeting, G01-1374~G01-1374, Seattle, WA, USA, May 2018
  9. J.G.Hwu*, C.F.Yang, and C.S.Liao, “Tunable Negative Differential Resistance in MISIM Structure with Ultra-thin Oxide and Designed Biasing,” WCSM 2018, 4th Annual World Congress of Smart Materials,, P.134~P.134, Osaka, Japan, Mar. 2018
  10. T.H.Li, C.S.Liao, and J.G.Hwu*, “Modulation of Minority Carriers in the C-V Characteristics of MIS Tunneling Diode by Surrounding MOS Capacitor,” 232nd ECS Meeting, D01-865~D01-865, National Harbor, MD (greater Washington, DC area), USA, Oct. 2017
  11. C.F.Yang and J.G.Hwu*, “Double Negative Differential Resistance Properties in MISIM Structure with Substrate Grounded and Simultaneous Biasing in Two Terminals,” 232nd ECS Meeting, D01-0826~ D01-0826, National Harbor, MD (greater Washington, DC area), USA, Oct. 2017
  12. C.F.Yang and J.G.Hwu*, “Double Negative Differential Resistance Properties in MISIM Structure with Substrate Grounded and Simultaneous Biasing in Two Terminals,” 232nd ECS Meeting, D01-0826~ D01-0826, National Harbor, MD (greater Washington, DC area), USA, Oct. 2017
  13. J.G.Hwu*, K.H.Tseng, Y.D.Tan, and C.S.Liao, “Transient Read Current for MIS(p) Tunnel Diode with Gate Electrode Surrounded by Ultra-Thin Metal,” Nano Science & Technology - Nano S&T 2017, P.373.~ P.373.(Invited), Fukuoka, Japan, Oct. 2017
  14. W.T.Hou, W.C.Kao, and J.G.Hwu*, “Enhancement of Light-to-Dark Current Ratio Via Coupling Effect for MIS (p) Tunnel Diode Photo Sensors,” 231th ECS Meeting, G02-1277~G02-1277, New Orleans, LA, USA,, May 2017
  15. C.J.Chou and J.G.Hwu*, “Rearrangement of Fringing Field By Sidewall Passivated Metal Gate in MIS Tunnel Diode,” 231th ECS Meeting, G02-1259~ G02-1259, New Orleans, LA, USA, May 2017
  16. M.H.Yang and J.G.Hwu*, “MIS(p) Saturation Tunneling Current Controlled By Neighboring MIS Inversion Level Via Coupling Effect,” 231th ECS Meeting, G02-1257~G02-1257, New Orleans, LA, USA, May 2017
  17. J.G.Hwu*, W.T.Hou, and C.S.Liao, “Voltage Drop Modulation and Fringing Field Effect Mechanism in MIS(p) Tunnel Diode for Sensing Application,” WCSM 2017, 3rd Annual World Congress of Smart Materials, P.145.~P.145. (Invited), Bangkok, Thailand,, May 2017
  18. J.G.Hwu*, “Si MIS Tunnel Diodes for Sensing Applications,” 6th International Symposium on Next Generation Electronics (ISNE, Track 3, 04, P.23.~P.23 (Invited), Keelung, Taiwan,, May 2017
  19. M.H.Yang and J.G.Hwu*, “Saturation Current Coupling Phenomenon in MIS(p) Tunnel Diodes,” International Electronic Devices and Materials Symposium - IEDMS 2016, PD-3~PD-3, National Taiwan Normal University, Taipei, Taiwan, ROC, Nov. 2016
  20. C.J.Chou and J.G.Hwu*, “Effect of Fringing Field on the Electrical Characteristics of MIS Tunnel Diode with Sidewall Passivated Metal Gate,” International Electronic Devices and Materials Symposium - IEDMS 2016, PD-4~PD-4, National Taiwan Normal University, Taipei, Taiwan, ROC, Nov. 2016
  21. W.T.Hou and J.G.Hwu*, “Photo Sensitivity Enhancement by Controlling Neighboring Device Inversion Level via Coupling Effect on MIS(p) Tunnel Diodes,” International Electronic Devices and Materials Symposium - IEDMS 2016, November 24-25 (Best Paper Award), D2-1~D2-1, National Taiwan Normal University, Taipei, Taiwan, ROC, Nov. 2016
  22. H.H. Lin and J.G. Hwu*, “Local Thinning Induced Less Oxide Breakdown in Mos Structures Due to Lateral Non-Uniformity Effect,” PRiME 2016/230th ECS Meeting, G02: Semiconductors, Dielectrics, and Metals for Nanoelectronics 14, G02-1808~G02-1808, Honolulu, Hawaii, USA, Oct. 2016
  23. C.S. Liao and J.G. Hwu*, “Current Coupling Effect in MIS Tunnel Diode with Coupled Open-Gated MIS Structure,” PRiME 2016/230th ECS Meeting, G02: Semiconductors, Dielectrics, and Metals for Nanoelectronics 14, G02-1810~G02-1810, Honolulu, Hawaii, USA, Oct. 2016
  24. J.G.Hwu*, C.S.Liao, and H.H.Lin,, “Coupling Effect between Nanoscale Oxide MOS Tunneling Diodes,” Nano Science & Technology - Nano S&T 2016 (Invited Talk), 404~404, Singapore, Oct. 2016
  25. J.G.Hwu*, C.S.Liao, and H.H.Lin, “Depletion Behavior in MIS Tunnel Diode for Sensing Application,” WCAM 2016, 5th Annual World Congress of Advanced Materials (Invited Talk), 161~161, Chongqing, China, Jun. 2016
  26. W.C. Kao, J.Y. Chen and J.G. Hwu, “Two States Phenomenon by Neighboring Device Coupling in MIS(p) Tunnel Current,” 229th ECS Meeting, Abstract No. D01-1007, San Diego, California, USA, May 2016
  27. J.Y. Chen, W.C. Kao, and J.G. Hwu, “Lateral Non-Uniformity Reduction By Compensatory Metal Embedded in Mos Structure with Ultra-Thin Anodic Oxide,” 229th ECS Meeting, Abstract No. D01-0993, San Diego, California, USA, May 2016
  28. W.C.Kao and J.G.Hwu, “Effects of Oxide Thickness and Neighboring Device Coupling on MIS(p) Tunnel Curren,” International Electronic Devices and Materials Symposium - IEDMS 2015, Paper No. B2-2., Kun Shan University, Tainan, Taiwan, ROC, Nov. 2015
  29. J.Y.Chen and J.G.Hwu, “Effect of Compensated Aluminum Embedded in MOS Structure on The Reduction of Lateral Oxide Non-uniformity,” International Electronic Devices and Materials Symposium - IEDMS 2015, Paper No. B1-4., Kun Shan University, Tainan, Taiwan, ROC, Nov. 2015
  30. P.K.Chang, and J.G.Hwu, “Reduction of Frequency Dispersion by Inserting Aluminum Layer between Aluminum Oxide and Silicon Oxide in 4H-SiC MOS Structure,” International Electronic Devices and Materials Symposium - IEDMS 2015, Paper No. B3-2, Kun Shan University, Tainan, Taiwan, ROC, Nov. 2015
  31. J.G.Hwu*, C.S.Liao, and H.C.Lin, “MIS(p) Tunnel Diode for Leakage Detection and Transconductance Application,” International Electronic Devices and Materials Symposium - IEDMS 2015, Paper No. B3, Kun Shan University, Tainan, Taiwan, ROC, Nov. 2015
  32. 8C.S.Liao and J.G.Hwu, “The Device-Perimeter Dependency in the Transient Current of a Metal-Insulator-Metal-Insulator-Semiconductor Capacitor with Anodic Oxide Films,” 228th ECS Meeting, Abstract No.55316, Phoenix, Arizona, USA, Oct. 2015
  33. H.H.Lin, Y.K.Lin, and J.G.Hwu*, “Non-uniform Hole Current Induced Negative Capacitance Phenomenon Examined by Photo-illumination in MOS(n),” 228th ECS Meeting, Abstract No. 56194, Phoenix, Arizona, USA, Oct. 2015
  34. C.F.Yang and J.G.Hwu*, “Tunneling Current Induced Frequency Dispersion in the C-V Behavior of Ultra-Thin Oxide Mos Capacitors,” 228th ECS Meeting, Abstract No. 55484, Phoenix, Arizona, USA, Oct. 2015
  35. C.S.Liao and J.G.Hwu*, “Negative Gate Transconductance in MIS Tunnel Diode Induced By Peripheral Minority Carrier Control Mechanism,” 228th ECS Meeting, Abstract No. 55313, Phoenix, Arizona, USA, Oct. 2015
  36. C.T.Yang and J.G.Hwu*, “Photosensing in MOS(p) and MOS(n) Photodiodes,” 2015 International Conference on Solid State Devices and Materials, ssdm 2015, Session No: PS. 7-11, Sapporo Convention Center, Sapporo, Japan, Sept. 2015
  37. J.G.Hwu* and H.W.Lu, “Photo Sensitivity Enhancement through Oxide Voltage Drop Modulation Mechanism in MOS Tunneling Diode,” 2015 EMN EAST MEETING – Energy Materials and Nanotechnology (Invited), Paper No. C12, Beijing, China, Apr. 2015
  38. C.K.Kao and J.G.Hwu*, “The Concave I-V Behavior in the Depletion Region of MOS Device with Al2O3-Al-SiO2 Stack Structure,” International Electronic Devices and Materials Symposium - IEDMS 2014, Session 13, Paper No. 1143, Fullon Hotel, Hualien, Taiwan, ROC, Nov. 2014
  39. P.K.Chang and J.G.Hwu*, “Effects of Illumination on Interface Properties of Al/SiO2/n-SiC MOS Structure,” International Electronic Devices and Materials Symposium - IEDMS 2014, Section 5, Paper No. 1342, Fullon Hotel, Hualien, Taiwan, ROC, Nov. 2014
  40. C.F.Yang and J.G.Hwu*, “CV Frequency Dispersion without Interface Trap in Ultra-thin Oxide MOS Structure,” International Electronic Devices and Materials Symposium - IEDMS 2014, Session 15, Paprer No. 1141, Fullon Hotel, Hualien, Taiwan, ROC, Nov. 2014
  41. Y.D.Tang and J.G.Hwu*, “A Transistor-less Memory Cell withPositive/Negative Read Current Transient Characteristic in MOS Structure,” International Electronic Devices and Materials Symposium - IEDMS 2014, Session 18, Paper No. 1124, Fullon Hotel, Hualien, Taiwan, ROC, Nov. 2014
  42. P.H.Tseng, Y.K.Lin, H.W.Lu, Y.C.Liao, and J.G.Hwu*, “Nanoscale Oxide Engineering on Si Substrate,” International Electronic Devices and Materials Symposium - IEDMS 2014, Plenary Session 1, PP.12-14, Fullon Hotel, Hualien, Taiwan, ROC, Nov. 2014
  43. Y.K.Lin and J.G.Hwu*, “Role of Lateral Diffusion Current in Gate Current Characteristics of MOS(p) and MOS(n) Capacitors with Ultrathin (< 3 nm) Oxides,” Nano Science & Technology - Nano S&T 2014, P.153. (invited), Qingdao, China, Oct. 2014
  44. C.S.Pang and J.G.Hwu*, “Improvement of the Breakdown Endurance of High-k HfO2 Dielectric by Stacking Technology,” 3rd International Symposium on Next-Generation Electronics (ISNE 2014), Paper No: 240115, Chang Gung University, Taoyuan, Taiwan, May 2014
  45. P.L.Hsu, C.C.Lin, L. Lin, C.W. Lee, and J.G.Hwu*, “Roles of Diffusion Current and Hole Tunneling Current in Non-uniform Current Conduction for MOS Tunneling Diodes in Inversion Region,” International Electronic Devices and Materials Symposium - IEDMS 2013, Section 5, Paper No.1., November 28-29, National Chi Nan University, Nantou, Taiwan, ROC, Nov. 2013
  46. H.H.Lin and J.G.Hwu*, “Investigation of Inversion Characteristics of Non-planar MOS Structures,” International Electronic Devices and Materials Symposium - IEDMS 2013, Section 5, Paper No.3., National Chi Nan University, Nantou, Taiwan, ROC., Nov. 2013
  47. C.S.Pang and J.G.Hwu*, “Improvement of the Sensitivity of Metal-Oxide-Semiconductor Photo Sensors by Hafnium Oxide/Silicon Dioxide Stack Structure,” International Electronic Devices and Materials Symposium - IEDMS 2013, Section 12, Paper No.1., National Chi Nan University, Nantou, Taiwan, ROC., Nov. 2013
  48. Y.C.Liao and J.G.Hwu*, “Investigation of the Non-uniformity Characteristics of MOS (p) and MOS (n) Structures through Deep Depletion Analysis,” International Electronic Devices and Materials Symposium - IEDMS 2013, Section 5, Paper No.2., National Chi Nan University, Nantou, Taiwan, ROC., Nov. 2013
  49. T.Y.Chen and J.G.Hwu*, “Sensitivity Enhancement of Metal-oxide-semiconductor Tunneling Photodiode with Trapped Electrons in Ultra-thin SiO2 Layer,” 224th ECS Meeting, Abstract No. 1963., San Francisco, California, USA,, Oct. 2013
  50. H.W.Lu and J.G.Hwu*, “Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region due to Edge Fringing Field Effect,” 224th ECS Meeting, Abstract No. 2188., San Francisco, California, USA, Oct. 2013
  51. C.M.Hsu and J.G.Hwu*, “High-k/SiC Structure Examined by Band Alignment Analysis and C-V Dispersion Behavior,” IEEE Nanotechnology Materials and Devices Conference - IEEE NMDC 2013, Paper No. TP-P1-2., National Cheng-Kung University, Tainan, Taiwan,, Oct. 2013
  52. J.G Hwu*, P.L.Hsu, L.Lin and C.W.Lee, “Edge-Dependent I-V Behavior of MOS(p) Structures with Ultrathin Oxides(< 3nm) under Inversion Region,” Nano Science & Technology - Nano S&T 2013, P.266., September 26-28, 2013, Xi’an, China (invited), Sept. 2013
  53. P.H.Tseng and J.G.Hwu*, “Interface Trap Redistribution and Deep Depletion Behavior in Non-planar MOS with Ultra-thin Oxide Grown by Anodic Oxidation,” 223rd ECS Meeting, Abstract No. E2-0772., Toronto, Ontario, Canada, May 2013
  54. C.C.Lin and J.G.Hwu*, “Sensitivity Enhancement of Metal-Oxide-Semiconductor Tunneling Temperature Sensor with Al2O3/SiO2 Dielectric Stacks,” 223rd ECS Meeting, No. J3-1508., Toronto, Ontario, Canada, Abstract, May 2013
  55. P.K.Chang and J.G.Hwu*, “Variations in Effective Areas of Depletion and Deep Depletion Regions from MOS C-V Curves,” International Electronic Devices and Materials Symposia - IEDMS 2012, Paper No. DP23., I-Shou University, Kaohsiung, Taiwan, ROC, Nov. 2012
  56. C.M.Hsu and J.G.Hwu*, “Detection of Carbon Interstitial Distribution of 4H-SiC Capacitors using AES and XPS Analysis,” International Electronic Devices and Materials Symposia - IEDMS 2012, Paper No. CO04., I-Shou University, Kaohsiung, Taiwan, ROC, Nov. 2012
  57. P.H.Tseng and J.G.Hwu*, “Stress Induced Interface Trap Capacitance Redistributions in Non-planar Substrate MOS Structures,” International Electronic Devices and Materials Symposia - IEDMS 2012, Paper No. DO13., I-Shou University, Kaohsiung, Taiwan, ROC, Nov. 2012
  58. C.M.Hsu and J.G.Hwu*, “SiO2 Thickness Dependency of C-V Dispersion in Stacked Al/HfO2/SiO2/4H-SiC Capacitors,” 221st ECS Meeting, Paper No. E1-695., Seattle, Washington, USA, May 2012
  59. P.H.Tseng and J.G.Hwu*, “Electrical Characterization of Al-SiO2-Si Capacitors with Non-p;anar Gate Oxides,” International Electronic Devices and Materials Symposia - IEDMS 2011, Paper No. D2-3., National Taiwan University of Science and Technology, Taipei, T, Nov. 2011
  60. J.C.Chiang and J.G.Hwu*, “Two-State Trap-Assisted Tunneling Current Characteristics of High-k/SiO2 Stacked Structure with High Bandgap Substrate,” International Electronic Devices and Materials Symposia - IEDMS 2011, Paper No. D3-2., National Taiwan University of Science and Technology, Taipei, Ta, Nov. 2011
  61. C.C.Lin and J.G.Hwu*, “Electrical Characteristics and Temperature Response of Al2O3 Gate Dielectrics with and without Nitric Acid Compensation,” 220h ECS Meeting, Paper No. E4-1920., Boston, MA, USA, Oct. 2011
  62. J.G.Hwu*, “Fringing Field Induced Deep Depletion in MOS Devices with Ultra-thin Gate Dielectrics,” IEEE Mini-Colloquia 2011, New Concept for Advanced Electronic Device, Presentation No. IV., I-Shou University, Kaohsiung, Taiwan , ROC., Oct. 2011
  63. C.Y.Wang, H.W.Lu, and J.G.Hwu*, “Photovoltaic Characteristics of MOS Structure with Photo Enhanced Trap Assist Tunneling Current by Oxide Etching,” IEEE International NanoElectronics Conference – 2011 IEEE INEC, Paper No. G3-12., Chang Gung University, Taiwan, Jun. 2011
  64. J.C.Chiang and J.G.Hwu*, “Two-State Current Conduction in High-k/SiO2 Stacked Dielectric with High Bandgap 4H-SiC Substrate,” 219th ECS Meeting, Paper No. E9-1484., Montreal, QC, Canada, May 2011
  65. T.Y.Chen, H.W.Lu and J.G.Hwu*, “Influence of Residual Ions and Gases at Si/SiO2 Interface in Ultra-Thin Gate Oxide,” 219th ECS Meeting, Paper No. E6-1340., Montreal, QC, Canada, May 2011
  66. H.W.Lu, T.Y.Chen and J.G.Hwu*, “Electrical Characteristics Analysis at Oxide Flat-band Voltage for Al-SiO2-Si Capacitor,” 219th ECS Meeting, Paper No. E7-04490., Montreal, QC, Canada, May 2011
  67. J.Y.Cheng, C.Y.Yang, and J.G.Hwu*, “Edge Field Enhanced Deep Depletion Phenomenon in MOS Structures with Ultra-thin Gate Oxides,” 10th International Conference on Solid State and Integrated Circuit Technology ICSICT’2010 (invited), Proceedings (part 2 of 3) PP.844, Shanghai, China., Nov. 2010
  68. C.M.Hsu and J.G.Hwu*, “Low-Temperature and Cost-Effective Al2O3 Prepared by Anodization in Ammonium Adipate Solution,” International Electronic Devices and Materials Symposia - IEDMS 2010, Paper No. D5-4., Kuva Chateau, Chung Li, Taiwan, ROC, Nov. 2010
  69. T.U.Chen, H.W.Lu, and J.G.Hwu*, “Improvement in the Reliability of Ultra-thin Gate Oxide by Room Temperature Vacuum Treatment,” International Electronic Devices and Materials Symposia - IEDMS 2010, Paper No. D4-5., Kuva Chateau, Chung Li, Taiwan, ROC, Nov. 2010
  70. H.W.Lu, T.U.Chen, and J.G.Hwu*, “A Novel Methodology to Extract Ultra-thin Dielectric Thickness (<1.8nm) by Analyzing Current Behavior at Oxide Flat-band Voltage,” International Electronic Devices and Materials Symposia - IEDMS 2010, Paper No. D4-6., Kuva Chateau, Chung Li, Taiwan, ROC, Nov. 2010
  71. J.Y.Cheng and J.G.Hwu*, ““Investigation of Illuminated High-Frequency Capacitance-Voltage Response in Deep Depletion of HfO2 and SiO2 MOS Capacitors with Ultra-thin Gate Oxides,” 2010 International Conference on Solid State Devices and Materials, SSDM 2010., P-3-19, PP.289-290., The University of Tokyo, Tokyo, Japan., Sept. 2010
  72. C.Y.Wang and J.G.Hwu*, “Trench Structure Metal-Oxide-Semiconductor (MOS) Solar Cells with Oxides Prepared by Anodization Technique,” The 15th OptoElectronics and Communications Conferences, OECC 2010, Technical Digest 7P-55, PP.366-3, Sapporo Convention Center, Sapporo, Japan., Jul. 2010
  73. C.Y.Yang, C.M.Hsu and J.G.Hwu*, “Sensitive MOS Photo-detector with Stacking Structure of SiO2/HfO2,” Symposium on Nano Device Technology, SNDT 2010 (invited), Abstract Digest, P.9, S1-1., Hsinchu, Taiwan, National Nano Device Laboratories, May 2010
  74. C.M.Hsu, C.Y.Yang, and J.G.Hwu*, “Characterization of 4H-SiC MOS Capacitor with Ultrathin Al2O3 Gate Dielectric Prepared by Sputtering in Oxygen Ambient,” International Electronic Devices and Materials Symposia - IEDMS 2009, Paper No.122, Chang Gung University, Kweishan, Taoyuan, Taiwan, ROC, Nov. 2009
  75. H.Y.Chiang and J.G.Hwu*, “Improvement in the Electrical Characteristics of Sputtered Al2O3 Dielectric Layers with the Compensation of Anodization in HNO3,” International Electronic Devices and Materials Symposia - IEDMS 2009, Paper No. 158., Chang Gung University, Kweishan, Taoyuan, Taiwan, ROC, Nov. 2009
  76. J.C.Chiang and J.G.Hwu*, “4H-SiC MOS Structure with Aluminum Oxide Stacked on Interfacial Oxide Prepared by UV Light-Assist Anodization,” International Electronic Devices and Materials Symposia - IEDMS 2009, Paper No. 133, Chang Gung University, Kweishan, Taoyuan, Taiwan, ROC, Nov. 2009
  77. J.Y.Cheng, C.T.Huang, and J.G.Hwu*, “Comparison of Lateral Non-uniformity Phenomena between HfO2 and SiO2 from Magnified C-V Curves in Inversion Region,” 216th ECS Meeting, PP.327-338, Vienna, Austria, Oct. 2009
  78. C.Y.Wang and J.G.Hwu*, “Characterization of Stacked Hafnium Oxide (HfO2)/Silicon Dioxide (SiO2) Metal-Oxide-Semiconductor (MOS) Tunneling Temperature Sensors,” 216th ECS Meeting, PP.361-370, Vienna, Austria, Oct. 2009
  79. C.Y.Yang and J.G.Hwu*, “Characteristics and Reliability of Low-Temperature Aluminum Oxide Dielectric Stacks Prepared by DC-Sputter of Aluminum Target Injected with Oxygen and Followed by Compensation in Nitric Acid,” Euro Nano Forum 2009 – Nanotechnology for Sustainable Economy, European and International Forum on Nanotechnology, Proceedings, P-116, Prague, Czech Republic, Jun. 2009
  80. J.C.Tseng* and J.G.Hwu, 2009, “Characterization of the Electrostatic Discharge Induced Interface Traps in Metal-Oxide-Semiconductor Field Effect Transistors,” 2009 IEEE International Reliability Physics Symposium, EL.6., Fairmont The Queen Elizabeth, Montreal, Quebec, Canada, Apr. 2009
  81. J.Y.Cheng, C.T.Huang and J.G.Hwu*, “Study on CV/IV Behaviors of the MOS Structure in Deep Depletion Region,” Symposium on Nano Device Technology, SNDT 2009, P.7, A1-1 (invited), Hsinchu, Taiwan, National Nano Device Laboratories, Apr. 2009
  82. C.M Hsu, K.C.Chuang, C.Y.Yang, and J.G.Hwu*, “Ultrathin Anodized Aluminum Oxide on 4H-SiC MOS Capacitors Grown in Ammonium Adipate Solution,” International Electronic Devices and Materials Symposia - IEDMS 2008, BO-504, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  83. H.L.Chen, C.J.Lee, and J.G.Hwu*, “Effect of Tensile Stress on MOS Capacitors with Ultra-thin Gate Oxides,” International Electronic Devices and Materials Symposia - IEDMS 2008, CO-437, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  84. P.K.Chang and J.G.Hwu*, “Determination of Ultrathin Oxide Thickness from Depletion Region of C-V Curves,” International Electronic Devices and Materials Symposia - IEDMS 2008, CO-525, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  85. C.H.Chang and J.G.Hwu*, “Characteristics of Metal-Al2O3-HfO2-Oxide-Silicon (MAHOS) Flash Devices Prepared by Cost-Effective in-situ Oxidation Method,” International Electronic Devices and Materials Symposia - IEDMS 2008, AO-502, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  86. C.Y.Yang, C.M Hsu, and J.G.Hwu*, “Low Temperature Tandem Al2O3 Gate Dielectrics Prepared by DAC-ANO Compensation in Nitric Acid,” International Electronic Devices and Materials Symposia - IEDMS 2008, BO-504, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  87. H.T.Lu and J.G.Hwu*, “Nonuniformity Characterization of MOS Structure with HfO2 Dielectric Layer Based on C-V Measurement in Deep Depletion Region,” International Electronic Devices and Materials Symposia - IEDMS 2008, CO-444, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  88. C.H.Chen and J.G.Hwu*, “Investigation of Low-Temperature-Processing Al2O3/Al-Si-O Gate Dielectrics Prepared by Nitric Acid Oxidation for MOS Devices,” International Electronic Devices and Materials Symposia - IEDMS 2008, CO-438, National Chung Hsing University, Taichung, Taiwan, ROC, Nov. 2008
  89. K.C.Chuang, C.M.Hsu, and J.G.Hwu*, “Frequency Dispersion in Capacitance-Voltage Characteristics in SiC MOS Capacitors,” International Electronic Devices and Materials Symposia - IEDMS 2008, BP-443, National Chung Hsing University, Taichung, Taiwan, Nov. 2008
  90. C.Y.Wang and J.G.Hwu*, “Low-Temperature Processing Metal-Oxide-Semiconductor (MOS) Structure Solar Cell Prepared by Cost-Effective Anodization Technique,” Fourth International Workshop on New Group IV Semiconductor Nanoelectronics, PP.11-12., Laboratory for Nanoelectronics and Spintronics, Research Institu, Sept. 2008
  91. Y.H. Shih, S.R.Lin, T.M.Wang, H.P.Lin, J.C.Tseng, and J.G.Hwu*,, “Temperature Sensing Application and Lateral Non-uniformity Phenomenon for MOS Capacitors with Ultra-thin Gate Oxides,” NSC-JST Nano Device Workshop, invited, National Taiwan University, Taipei, Taiwan, Republic of China., Jul. 2008
  92. S.J.Chang, T.M.Wang, and J.G.Hwu*, ““Investigation of the Mechanism of Negative Capacitance Occurred in MOS Capacitors with Ultra-thin Oxides on N-type Substrates,” Proceedings of International Electronic Devices and Materials Symposium - IEDMS 2007, National Tsing-Hua University, Hsinchu, Taiwan, Republic of Chin, Dec. 2007
  93. P.K.Chang and J.G.Hwu*, “Application Boundary for Ultrathin Oxide Thickness Determination by Linear Regression Technique,” Proceedings of International Electronic Devices and Materials Symposium - IEDMS 2007, National Tsing-Hua University, Hsinchu, Taiwan, Republic of Chin, Dec. 2007
  94. C.H.Chang and J.G.Hwu*, “Low Temperature (Tmax=380 0C) Ultra-thin Hafnium Oxide Stacks with Terraced Structures on A Single Wafer by Sputtering of Hf Metal on Tilted Substrate Followed by Nitric Acid Oxidation,” Proceedings of International Electronic Devices and Materials Symposium - IEDMS 2007, National Tsing-Hua University, Hsinchu, Taiwan, Republic of Chin, Dec. 2007
  95. K.C.Chuang and J.G.Hwu*, “Reduction of Oxide Charge and Interface-Trap Density in Silicon Oxide on N-Type 4H-SiC Prepared by Scanning Frequency Anodization Method,” Proceedings of International Electronic Devices and Materials Symposium - IEDMS 2007, National Tsing-Hua University, Hsinchu, Taiwan, Republic of Chin, Dec. 2007
  96. C.N.Lin, Y.L.Yang, W.T.Chen, S.C.Lin, and J.G.Hwu*, “Investigation of Strain-Temperature Stress Effects on the Characteristics of MOS Capacitors with Ultra-thin Gate Oxides,” IEEE International Conference on Electron Devices and Solid-State Circuits, Tayih Landies Hotel, Tainan, Taiwan, Republic of China., Dec. 2007
  97. K.C.Chuang and J.G.Hwu*, “Silicon oxide Gate Dielectric on N-Type 4H-SiC Prepared by Low Thermal Budget Anodization Method,” International Conference on Solid State Devices and Materials (SSDM2007), G-6-5, PP.808-809, Tsukuba, Japan, Sept. 2007
  98. C.H.Chang and J.G.Hwu*, “Low Temperature Ultra-thin Hafnium Oxide Dielectrics by Sputtering of Hf Metal on Tilted Substrate Followed by Nitric Acid Oxidation then Anodization Compensation in D. I. Water,” International Conference on Solid State Devices and Materials (SSDM2007), F-5-4, PP.780-781, Tsukuba, Japan, Sept. 2007
  99. K.C.Chuang and J.G.Hwu*, “Electrical Characteristics of Silicon Oxide Film Grown by Anodic Oxidation in Nitric Acid at Low Temperature,” Proceedings of International Electronic Devices and Materials Symposium, Vol. B & C, PP.112-113, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006
  100. C.H.Chang, and J.G.Hwu*, “Anodic Oxidation (ANO) Compensation Effect on The Leakage Reduction of Low Temperature High-k Al2O3 Dielectrics as Prepared byTilted Evaporation of Aluminum Followed by Nitric Acid Oxidation,” Proceedings of International Electronic Devices and Materials Symposium, Vol. A & D, PP.252-253, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006
  101. H.P.Lin and J.G.Hwu*, “Using QM-based Terman method as a direct index of the Lateral Nonuniformities of Charges in the Dielectric Layer of MOS Capacitors,” Proceedings of International Electronic Devices and Materials Symposium, Vol. A & D, PP.297-298, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006
  102. Y.L.Yang, C.H.Chang, Y.H.Shih, K.Y.Hsieh, and J.G.Hwu*, “Hydrogen Eraser for Tightening VT Distribution of Nitride Trapping Memory,” Proceedings of International Electronic Devices and Materials Symposium, Vol. A & D, PP.303-304, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006
  103. P.K.Chang, and J.G.Hwu*, “Ultrathin Gate Oxide Thickness (<2.0 nm) Extraction TechniqueBased on Low Dissipation Factor Regions of MOS C-V Curves,” Proceedings of International Electronic Devices and Materials Symposium, Vol. A & D, PP.42-45, National Cheng-Kung University, Tainan, Taiwan, Republic of Chin, Dec. 2006
  104. J.G. Hwu*, “Silicon MOS Structures with Ultra-Thin Gate Dielectrics,” The Conference on the Micro/Nano Technology between Taiwan and Scotland, PP.22-30, National Formosa University, Fu-Wei, Yun-Lin, Taiwan, Dec. 2006
  105. T.M. Wang, S.J. Chang and J.G. Hwu*, “Comparison of Suboxide Characteristics for Ultra-thin Silicon Oxides Grown on N- and P-type Substrates Simultaneously,” Proceedings of Electronic Devices and Materials Symposium, Paper No.CO15, I-Shou University, Kaohsiung, Taiwan, Republic of China, Nov. 2005
  106. T.H. Li and J.G. Hwu*, “Reduction in Leakage Current in Ultra-thin Gate Oxides by Tensile-Stress Anodization,” Proceedings of Electronic Devices and Materials Symposium, Paper No.CO17, I-Shou University, Kaohsiung, Taiwan, Republic of China, Nov. 2005
  107. H.P. Lin and J.G. Hwu*, “Direct Observation of the Lateral Nonuniformities of Charges in the Dielectric Layer of MOS Capacitors by Terman Method,” Proceedings of Electronic Devices and Materials Symposium, Paper No. AO05, I-Shou University, Kaohsiung, Taiwan, Republic of China, Nov. 2005
  108. C.H. Chang and J.G. Hwu*, “Application of the Direct Superimposed with Alternative Current Anodic Oxidation (DAC-ANO) Compensation Technique to Improve the Quality and Electrical Characteristics of Devices with High-k Gate Dielectrics,” Proceedings of Electronic Devices and Materials Symposium, Paper No. CO13, I-Shou University, Kaohsiung, Taiwan, Republic of China, Nov. 2005
  109. C.H. Chang, T.M. Wang, and J.G. Hwu*, “Quality Improvement and Electrical characteristics of High-k Films after Receiving Direct Superimposed with Alternative Current Anodic Oxidation (DAC-ANO) Compensation,” 208th Meeting of The Electrochemical Society, Paper No.550, Westin Bonaventure, Los Angeles, California, USA, Oct. 2005
  110. S.W. Huang and J.G. Hwu*, “Indication of Lateral Nonuniformity of Effective Oxide Charges in High-k Gate Dielectrics by Terman’s Method,” 208th Meeting of The Electrochemical Society, Paper No.577, Westin Bonaventure, Los Angeles, California, USA, Oct. 2005
  111. J.G. Hwu*, “Process and Application of Silicon MOS Structures with Ultra-Thin Gate Dielectrics,” Scotland-Taiwan Hi-Tech Forum: Micronanotechnology Workshop, (invited), The Royal Society of Edinburgh, Edinburgh, Scotland, Oct. 2005
  112. T.M. Wang and J.G. Hwu*, “Temperature-Induced Voltage Drop Rearrangement and Its Effect on Oxide Breakdown in MOS Capacitor Structure,” International Electronic Devices and Materials Symposium,, PP.319-322, December 20-23, Shin-Chu, Taiwan, Republic of China, Dec. 2004
  113. C.H. Chang, L.S. Lee, M.J. Tsai, and J.G. Hwu*, “Electrical characteristics of high-k HfO2 gate dielectrics prepared by oxidation in HNO3 followed by rapid thermal annealing in N2,” International Electronic Devices and Materials Symposium, PP.95-98, December 20-23, Shin-Chu, Taiwan, Republic of China, Dec. 2004
  114. J.G. Hwu*, “Thin Gate Dielectrics – Process and Application,” IMEC-Taiwan NSC Workshop on Nanotechnology on the occasion of IMEC’s 20th Anniversary,, (invited talk), September 24, Leuven, Belgium, Sept. 2004
  115. C.S.Kuo, L.S.Lee, M.J.Tsai, and J.G.Hwu*, “Ultra-thin HfO2 Gate Dielectrics Prepared by Oxidation of Hf Metal Film in Nitric Acid Followed by High Temperature Anneal,” International Symposium on Nanoelectronic Circuits and Giga-scale Systems (ISNCGS 2004), PP.51-55, February 12-13, Miao-Li, Taiwan, Feb. 2004
  116. Y.P.Lin and J.G.Hwu*, “MOS Tunneling Diodes with Ultra-thin Oxides of N-type and P-type Silicon Substrates,” International Symposium on Nanoelectronic Circuits and Giga-scale Systems (ISNCGS 2004), PP.56-60, February 12-13, Miao-Li, Taiwan, Feb. 2004
  117. S.W.Huang, H.L Tsai, J.R.Yang, C.W.Hsu, C.W.Hsiung, and J.G.Hwu*, “Alternative Nano-Scale Gate Dielectric on 4H-SiC Prepared by Low Thermal Budget Nitric Acid Oxidation of Ultra-thin Aluminum Film,” International Symposium on Nanoelectronic Circuits and Giga-scale Systems (ISNCGS 2004), PP.35-39, February 12-13, Miao-Li, Taiwan, Feb. 2004
  118. Y.P.Lin and J.G.Hwu*, “The Role of Suboxide in N-type and P-type MOS Diodes,” Proceedings of Electronic Devices and Materials Symposium, PP.783-786, Keelung, Taiwan, Nov. 2003
  119. S.W Huang, C.W Hsu , C.W Hsiung, and J.G Hwu*, “Process Technologies of SiO2 and Al2O3 Gate Dielectrics on 4H-SiC,” Proceedings of Electronic Devices and Materials Symposium, PP.791-794, Keelung, Taiwan, Nov. 2003
  120. C.S Kuo, J.F Hsu, and J.G Hwu*, “Characterization of Metal-Insulator-Semiconductor Structure with High-k Al2O3 Gate Dielectrics,” Proceedings of Electronic Devices and Materials Symposium, PP.681-684, Keelung, Taiwan, Nov. 2003
  121. T.M Wang,S.R Lin and J.G Hwu*, “MOS Tunneling Temperature Sensors for Detecting The On-chip Temperature Distribution,” Proceedings of Electronic Devices and Materials Symposium, PP.753-756, Keelung, Taiwan, Nov. 2003
  122. H.P Lin and J.G Hwu*, “Observation of The Change of Current Uniformities of MOS(P) Structures with Oxides Grown from 7400C to 8400C,” Proceedings of Electronic Devices and Materials Symposium, PP.734-737, Keelung, Taiwan, Nov. 2003
  123. Y.P.Lin and J.G.Hwu*, “Rapid Thermal and Anodic Oxidations of LPCVD Silicon Nitride Films,” 203 Meeting of The Electrochemical Society, De Palais des Congres, G1-Seventh International Symposium on Sil, 2003
  124. S.R.Lin and J.G. Hwu*, “High Sensitive MOS Tunneling Temperature Sensors for On-Chip Temperature Detection,” Proceedings of 2002 International Electron Devices and Materials Symposia, PP.469-472, Taipei, Taiwan, Republic of China, Dec. 2002
  125. Y.P Lin and J.G. Hwu*, “Low Interface States Al2O3/SiO2 Stacked Dielectric Structure with One Step Anodic Oxidation Followed by Rapid Thermal Annealing,” Proceedings of 2002 International Electron Devices and Materials Symposia, PP.94-97, Taipei, Taiwan, Republic of China, Dec. 2002
  126. S.W. Huang and J.G. Hwu*, “Characterization of MOS Structure with Aluminum Oxide Gate Dielectric,” Proceedings of 2002 International Electron Devices and Materials Symposia, PP.429-432, Taipei, Taiwan, Republic of China, Dec. 2002
  127. Y. P. Lin, Z. H. Chen, and J. G. Hwu*, “SiO2/Si Suboxide Characteristics of Ultra-Thin Gate Oxides Prepared by Room Temperature Anodic Oxidation and Rapid Thermal Oxidation,” International Conference on Solid State Devices and Materials, PP.708-709, Nagoya Congress Center, Tokyo, Sept. 2002
  128. Y.P.Lin and J.G.Hwu*, “Ultrathin Aluminum Oxide Gate Dielectric Prepared by Anodization Followed by Rapid Thrmal Anneal,” 201st Meeting of The Electrochemical Society, Centennial Meeting, Volume 2002-1, A, Philadelphia, USA, May 2002
  129. C.C.Hong nad J.G.Hwu*, “The Wafer Cutting Effect on the Substrate Injection Current of MOS Devices,” Proceedings of Electronic Devices and Materials Symposium, PP.33-36, Kaohsiung, Taiwan, Dec. 2001
  130. Y.P.Lin and J.G.Hwu*, “Ultra-thin Aluminum Oxide Gate Dielectric Prepared by Anodization,” Proceedings of Electronic Devices and Materials Symposium, PP.798-799, Kaohsiung, Taiwan, Dec. 2001
  131. Y.H.Shih and J.G.Hwu*, “A Polarity Dependent Breakdown Model of Ultra-thin Gate Oxides,” Proceedings of Electronic Devices and Materials Symposium, PP.46-49, Kaohsiung, Taiwan, Dec. 2001
  132. C.C.Hong and J.G.Hwu*, “Repeated Pulse-Heating Process in Rapid Thermal System,” The 5th Nano Engineering and Micro System Technology Workshop, Shin-Chu, Taiwan, Dec. 2001
  133. J.G.Hwu*, C.Y.Lee, C.C.Ting, and W.L.Chen, “Novel Ultra Thin Gate Oxide Growth Technique by Alternating Current Anodization,” 6th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Volume 1,PP.309-, Shanghai, China, Oct. 2001
  134. J.G. Hwu* and Y.H. Shih, “Utilizing an MOS Tunneling Diode as an On-Chip Temperature Sensing Device,” Tenth Canadian Semiconductor Technology Conference, P.139, Chateau Laurier Hotel, Ottawa, Canada, Aug. 2001
  135. J.G. Hwu*, “Application of Novel Oxidation to Prepare Si Nanostructure Devices,” 2001 NSC-NRC Workshop on Nano Device Technology and Nano Electronics, P.10. (invited), Sussex Drive, Room 3001, Ottawa, Canada, Aug. 2001
  136. C.C.Hong, C.Y.Chang, C.H.Chen, and J.G.Hwu*, “Repeated Spike Technology Employed in Rapid Thermal Processing,” International Conference on Solid State Devices and Materials, PP.166-167, Tokyo,Diamond Hotel, A-4-2, 2001
  137. C.H. Chen and J.G. Hwu*, “Silicon MOS Solar Cells with Oxide Prepared by Room Temperature Anodization in Saturated Hydrofluosilicic Acid (H2SiF6) Solution,” Proceedings of 2000 International Electron Devices and Materials Symposia Chung-Li, PP.121-124, Taiwan, Republic of China, Symposium A, Dec. 2000
  138. J.Y. Yen and J.G. Hwu*, “Stress Effect on the Kinetics of Silicon Thermal Oxidation,” Proceedings of 2000 International Electron Devices and Materials Symposia, PP.198-201, Chung-Li, Taiwan, Republic of China, Symposium A, Dec. 2000
  139. C.H. Hung and J.G. Hwu*, “Role of Interface Trap Generation in the Low-Voltage Tunneling Current (LVTC) Characteristics of Ultra-Thin Gate Oxide (~2nm) under High Field Stress,” Proceedings of 2000 International Electron Devices and Materials Symposia, PP.90-93, Chung-Li, Taiwan, Republic of China, Symposium A, Dec. 2000
  140. Y.R. Yen, J.L. Su, and J.G. Hwu*, “Improvement in Rapid Thermal Oxide Thickness Uniformity by the Control of Gas Flow,” Proceedings of 2000 International Electron Devices and Materials Symposia, PP.109-112, Chung-Li, Taiwan, Republic of China, Symposium A, Dec. 2000
  141. Y.H. Shih and J.G. Hwu*, “Degradation of Silicon near SiO2/Si Interface with Time after Post Oxidation Anneal (POA),” Proceedings of 2000 International Electron Devices and Materials Symposia, PP.31-34, Chung-Li, Taiwan, Republic of China, Symposium A, Dec. 2000
  142. C.C. Hong, T.Y. Lee, and J.G. Hwu*, “Application of Repeated Spike Oxidation (RSO) Technology to Thin Gate Oxide Growth,” Proceedings of 2000 International Electron Devices and Materials Symposia Chung-Li, PP.125-128, Taiwan, Republic of China, Symposium A, Dec. 2000
  143. C.H. Huang and J.G. Hwu*, “The Breakdown Properties of Front- and Back-side Post Oxidation Annealed (POA) Ultrathin Gate Oxide (<3 nm) under High Field Stress,” Proceedings of Electronic Devices and Materials Symposium, PP.527-530, Taoyuan, Taiwan, Republic of China, Dec. 1999
  144. Y.H. Shih and J.G. Hwu*, “Improvement of Thin Gate Oxide’s Reliability by Current Stress Followed by Rapid Thermal Annealing,” Proceedings of Electronic Devices and Materials Symposium, PP.531-534, Taoyuan, Taiwan, Republic of China, Dec. 1999
  145. C.C. Ting and J.G. Hwu*, “Characteristics of Ultra-thin Gate Oxides ( ~ 3 nm) Prepared by Anodization in Deionized Water and Then Followed by High Temperature Anneal,” Proceedings of Electronic Devices and Materials Symposium, PP.37-40, Taoyuan, Taiwan, Republic of China, Dec. 1999
  146. Y.H. Yeh and J.G. Hwu*, “Effect of Irradiation then Post Oxidation Annealing on Thin Gate Oxide,” Proceedings of Electronic Devices and Materials Symposium, PP.59-60, Taoyuan, Taiwan, Republic of China, Dec. 1999
  147. J.L. Chen, C.C. Hong, Y.R. Yen, and J.G. Hwu*, “Improvement in Rapid Thermal Thin Oxide Uniformity by Low Pressure Oxidation,” Proceedings of Electronic Devices and Materials Symposium, PP.159-162, Taoyuan, Taiwan, Republic of China, Dec. 1999
  148. J.Y. Yen and J.G. Hwu*, “Effect of Mechanical Stress on Thermal Oxidation of Silicon,” Proceedings of Electronic Devices and Materials Symposium, PP.115-118, Taoyuan, Taiwan, Republic of China, Dec. 1999

Patents:

  1. Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, and Chi-Wen Liu,, “Methods of Forming An Interconnect Structure Using A Self-Ending Anodic Oxidation,” U.S.A. Patent, Patent No.: US 9,812,395 B2, Nov. 2017
  2. Jenn-Gwo Hwu, Samuel C. Pan, and Chien-Shun Liao, “Double Exponential Mechanism Controlled Transistor,” U.S.A. Patent, Patent No.: US 9,748,379 B2, Aug. 2017
  3. Jenn-Gwo Hwu, Wei-Cheng Tian, and Po-Hao Tseng, “Systems and Methods for Forming Nanowires Using Anodic Oxidation,” U.S.A. Patent, Patent No.: US 9,528,194 B2, Dec. 2016
  4. 陳姿妤, 胡振國, “金氧半結構的記憶體元件及其製造方法,” 中華民國專利 —證書號-發明第 I 467754號, Jan. 2015
  5. 江榮進,胡振國, “具雙層陷阱之記憶體結構及其形成方法,” 中華民國專利 —證書號-發明第I425596號, Feb. 2014
  6. 呂涵薇, 胡振國, “測量氧化層厚度的方法,” 中華民國專利 —證書號-發明第I426576, Feb. 2014
  7. 胡振國, 莊凱傑, “於碳化矽基板上形成絕緣層之方法、碳化矽電晶體及其製造方法,” 中華民國專利 —專利編號-200903807, 申請案號-096125183, 2009
  8. Jenn-Gwo Hwu, and Kai-Chieh Chuang, “Silicon Carbide Methods for Fabricating The Same,” U.S.A. Patent — IPC8 Class: AHO1L2924F1, 20090014730, 2009
  9. Jenn-Gwo Hwu, Yen-Po Lin, and Szu-Wei Huang, “High-k Gate Dielectrics Prepared by Liquid Phase Anodic Oxidation,” U.S.A., Patent No.-6887310 B2, May 2005
  10. 胡振國, 郭智昇, 黃思維, “利用硝酸氧化技術製造金屬氧化層之方法,” 中華民國專利, 證書號-發明第I232893號, May 2005
  11. 李隆盛, 曾培哲, 郭智昇, 胡振國, “金氧半電晶體之高介電值閘極介電層的製造方法,” 中華民國專利, 證書號-發明第I228789號, Mar. 2005
  12. Lurng-Shehng Lee, Pei-Jer Tzeng, Chih-Sheng Kuo, and Jenn-Gwo Hwu, “Process of Forming High-K Gate Dielectric Layer for Metal Oxide Semiconductor Transistor,” U.S.A. Patent No. - 6991989 B2, May 2004
  13. 胡振國, 林彥伯,黃思維, “以液相陽極氧化技術成長高介電常數閘極介電質之方法,” 中華民國專利 —公告號-565885, 卷/期-019/012, 申請案號-091112489,, Dec. 2003
  14. 胡振國, 施彥豪, “金氧半穿隧二極體溫度感應器及其製造方法,” 中華民國專利 –公告號-530422, 卷/期-019/012, 申請案號-090127083,, 2003
  15. Jenn-Gwo Hwu and Yen-Hao Shih, “Method for Improving The Electrical Properties of A Gate Oxide,” U.S.A. Patent —Issued / Filed Dates – March 5, 2002 / February, 2002
  16. 胡振國, 施彥豪, “強化閘極氧化層之方法,” 中華民國專利 —公告號-417199, 卷/期-, 申請案號-088109723, 公告日, 2001
  17. 胡振國, 李國忠, 張鴻淵, “適用於快速熱處理系統之溫度補償法,” 中華民國專利 —公告號-388086, 卷/期-027/012, 申請案號-86105515,, 2000
  18. Jenn-Gwo Hwu, Kuo-Chung Lee, Hong Chang, and Chien-Lung Chen, “A Rapid Thermal Processor for Heating A Substrate,” U.S.A. Patent —Issued / Filed Dates – July 18, 2000 / Jan. 8,, 2000
  19. Jenn-Gwo Hwu, Kuo-Chung Lee, and Hong-Yuan Chang, “Temperature Compensation Method for Semiconductor Wafers in Rapid Thermal Processor Using Separated Heat Conducting Rings as Susceptors,” U.S.A. Patent — Issued / Filed Dates – July 20, 1999 / July 8,, 1999
  20. 胡振國, 鄭明哲, “藉陽極氧化及後續之高溫快速熱密化於矽基材上成長二氧化矽層的方法,” 中華民國專利 —公告號-328148, 卷/期-025/008, 申請案號-86102913,, 1998
  21. Jenn-Gwo Hwu and Ming-Jer Jeng, “Method for Making A Silicon Dioxide Layer on A Silicon Substrate by Pure Water Anodization Followed by Rapid Thermal Densification,” U.S.A. Patent —Issued / Filed Dates-April 7, 1998 / March 20, 1, 1998
  22. Wei-Shin Lu and Jenn-Gwo Hwu, “Method for Manufacturing Fluorinated Gate Oxide Layer,” U.S.A. Patent — Issued / Filed Dates-Nov. 4, 1997 / Dec.1, 1995, 1997
  23. 沈義斌, 吳正洲, 胡振國, “金屬絕緣半導體(MIS)太陽能電池及其絕緣層之製備方法,” 中華民國專利 —公告號-301063, 卷/期-024/009, 申請案號-85103236,, 1997
  24. Ming-Jer Jeng and Jenn-Gwo Hwu, “Method for Making A Fluorinated Silicon Dioxide Layer on Silicon Substrate by Anodic Oxidation at Room Temperature,” U.S.A. Patent — Issued / Filed Dates-April 1, 1997 / May 1, 199, 1997
  25. 鄭明哲, 胡振國, “藉室溫陽極氧化於矽基材上成長含氟二氧化矽層之方法,” 中華民國專利 —公告號-288177, 卷/期-023/029, 申請案號-85103918,, 1996
  26. Jenn-Gwo Hwu, Wei-Cheng Tian, and Po-Hao Tseng, “Systems and Methods for Forming Nanowires Using Anodic Oxidation,” USA (pending)
  27. Jenn-Gwo Hwu and Wei-Cheng Tian, “Antifuse Array and Method of Forming Antifuse Using Anodic Oxidation,” USA (pending)
  28. Jenn-Gwo Hwu and Wei-Cheng Tian, “Low-K Interconnect Structure and Forming Method Thereof,” USA (pending)
  29. Jenn-Gwo Hwu and Chien-Shun Liao, “Double Exponential Mechanism Controlled Transistor,” USA (pending)

other:

  1. J.G.Hwu, “Research and Development of Micro Electronics Division (1/3),” Sept. 2006, NSC94-2217-E-002-016
  2. J.G.Hwu, “Study of Advanced CMOS Devices and Processes (1/3),” May 2006, NSC94-2215-E-002-047
  3. J.G.Hwu, “Technologies of Forming High Quality Insulating Films for Low Substrate Temperature Process (1/3),” May 2006, NSC94-2215-E-002-044
  4. J.G.Hwu, “Process Development of Ultra-thin Gate Dielectrics and Novel Device Applications of Silicon MOS Structure (1/3),” May 2005, NSC93-2215-E-002-016
  5. J.G.Hwu, “Study on the Oxide Uniformity and Stress Effect in Rapid Thermal Processing (3/3)”,” May 2005, NSC93-2215-E-002-001
  6. 胡振國、 劉致為、吳又麟、林彥伯、黃思維、王宗苗、楊宜霖、郭智昇、張嘉華、陳自強、李秋宗、詹孫戎、魏潔瑩、陳博文, “矽新型元件及模組技術研發(3/3),” Sept. 2004, 奈米國家型科技計畫成果發表會暨台灣奈米科技展, September 6~8, Taipei, Taiwan, DE-2-6, PP.340~348.
  7. J.G.Hwu, “Study on The Oxide Uniformity and Stress Effect in Rapid Thermal Processing (2/3),” Jul. 2004, NSC92-2215-E-002-005
  8. J.G.Hwu, “Application of Ultra-thin Film Oxidation Technology on Si Devices (3/3),” Jul. 2004, NSC92-2120-E-002-005
  9. J.G.Hwu, “Development of Si Novel Devices and Module Technology (3/3),” Jul. 2004, NSC92-2120-E-002-004
  10. 胡振國、 劉致為、吳又麟、林彥伯、黃思維、郭智昇、林見儒、洪朝基、鄭容裕、林豪鵬、許博欽、林式庭, “矽新型元件及模組技術研發(2/3),” Nov. 2003, 奈米國家型科技計畫 – 商機探討暨成果發表會, November 8~10, Hsinchu, Taiwan, A-2-9-1~8, PP.117~118.
  11. J.G.Hwu, “Development of Si Novel Devices and Module Technology (2/3),” May 2003, NSC91-2120-E-002-001
  12. J.G.Hwu, “Application of Ultra-thin Film Oxidation Technology on Si Devices (2/3),” May 2003, NSC91-2120-E-002-002
  13. J.G.Hwu, “Study on The Oxide Uniformity and Stress Effect in Rapid Thermal Processing (1/3),” May 2003, NSC91-2215-E-002-023
  14. J.G.Hwu, “矽新型元件及模組技術研發(1/3) – 總計畫,” 2003, 工程科技通訊 (Engineering Science & Technology Newsletter NSC), 電機 第六十七期, PP.67-73. (invited)
  15. J.G.Hwu, “on Rapid Thermal Equipment and Process (3/3),” Sept. 2002, NSC90-2212-E-002-224
  16. J.G.Hwu, “Repeated Pulse-Heating Process in Rapid Thermal System (3/3),” Sept. 2002, NSC90-2212-E-002-225
  17. J.G.Hwu, “Development of Si Novel Devices and Module Technology (1/3),” May 2002, NSC90-2215-E-002-032
  18. J.G.Hwu, “Application of Ultra-thin Film Oxidation Technology on Si Devices (1/3),” May 2002, NSC90-2215-E-002-033
  19. J.G.Hwu, “Application of Oxidation in Liquid and Irradiation Technique to the Fabrication Process of Ultra-thin Gate Oxides,” Sept. 2001, NSC89-2215-E-002-042
  20. J.G.Hwu, “Studies on Rapid Thermal Equipment and Process (2/3),” May 2001, NSC89-2218-E-002-084
  21. J.G.Hwu, “Repeated Pulse-Heating Process in Rapid Thermal System (2/3),” May 2001, NSC89-2218-E-002-085
  22. J.G.Hwu, “Temperature Uniformity Compensation Technology for Wafers in Rapid Thermal Processor,” Oct. 2000, Knowledge Bridge (知識創新), No.4, October, P.2, (invited)
  23. J.G.Hwu, “A Study of the Process Development for Reliable Ultra-thin Gate Oxide with Low Leakage Property,” Sept. 2000, NSC89-2215-E-002-010
  24. J.G.Hwu, “Studies on Rapid Thermal Equipment and Process (1/3),” May 2000, NSC89-2218-E-002-018
  25. J.G.Hwu, “Repeated Pulse-Heating Process in Rapid Thermal System (1/3),” May 2000, NSC89-2218-E-002-016
  26. J.G.Hwu, “快速熱氧化層製程對厚度均勻度及電特性影響之研究,” 2000, 工程科技通訊 (Engineering Science & Technology Newsletter NSC), 電機 第五十期, (invited)
  27. J.G.Hwu, “A Study of the Automation of Rapid Thermal Process (III),” Sept. 1999, NSC88-2218-E-002-009
  28. J.G.Hwu, “The Development of the IC Key Equipment (III),” Sept. 1999, NSC88-2218-E-002-014
  29. J.G.Hwu, “A Study of the Effect of Rapid Thermal Oxidation Process on Oxide’s Thickness Uniformity and Electrical Property,” Aug. 1999, NSC88-2215-E-002-026
  30. J.G.Hwu, “Process Development of Ultra-thin Gate Dielectrics and Novel Device Applications of Silicon MOS Structure (2/3),” NSC94-2215-E-002-004