陳信樹教授的著作列表 - Publication List of Hsin-Shu Chen

Publication List of 陳信樹 Hsin-Shu Chen

Journal articles & book chapters:

  1. Yao-Sheng Hu, Li-Yu Huang, and Hsin-Shu Chen, “A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System,” IEEE Journal of Solid-State Circuits, Vol. 54, No. 10, pp. 2680-2690~2690, Oct. 2019
  2. Pang-Jung Liu, Rui-Min Lin, and Hsin-Shu Chen, “Two-Input Floating Buck Converter with Variable Off-Time Control Scheme for High-Efficiency and -Accuracy LED Lighting,,” IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 6, No. 2, pp. 563-570~570, Jun. 2018
  3. Pang-Jung Liu, Yu-Min Lai, Ping-Chieh Lee, and Hsin-Shu Chen, “A Fast-Transient DC-DC Converter with Hysteresis Prediction Voltage Control,” IET Transactions on Power Electronics, Vol. 10, No. 3, pp. 271-278~278, Mar. 2017
  4. Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, and Hsin-Shu Chen, “A 12.5fJ/conversion-step 8-bit 800 MS/s Two-Step SAR ADC,” IEEE Trans. on Circuits and Systems-II: Express Briefs Paper, Vol. 63, No. 12, pp.1166-1170~1170, Dec. 2016
  5. Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, and Hsin-Shu Chen, “An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique,” IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 63, No. 5, pp. 683-692, May 2016
  6. Chien-Jian Tseng, Chieh-Fan Lai, and Hsin-Shu Chen, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration,” IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 61, No. 10, pp. 2805-2815, Oct. 2014
  7. Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, and Hsin-Shu Chen, “A 6-bit 1 GS/s Two-Step SAR ADC in 40 nm CMOS,” IEEE Trans. on Circuits and Systems-II: Express Briefs Paper, Vol. 61, No. 5, pp. 339-343, May 2014
  8. Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, and Hsin-Shu Chen, “A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC,” IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 60, No. 11, pp. 2902-2910, Nov. 2013
  9. Pang-Jung Liu, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, and Yi-Jan Emery Chen, “Spur-Reduction Design of Frequency-Hopping DC-DC Converters,” IEEE Transactions on Power Electronics, Vol. 27, No. 11, pp. 4763-4771, Nov. 2012
  10. Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, and Hsin-Shu Chen, “A 10-bit 320MS/s Stage-Gain-Error Self-Calibration Pipeline ADC,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 6, pp. 1334-1343, Jun. 2012
  11. Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, and Yi-Jan Emery Chen, “A High-Efficiency CMOS DC-DC Converter with 9-μs Transient Recovery Time,” IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 59, No. 3, pp. 575-583, Mar. 2012
  12. Hsin-Shu Chen, and Jyun-Cheng Lin, “A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop,” IEICE Transactions on Electronics, Vol. E93-C, No. 6, Jun. 2010
  13. Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Jacky Hong, Chun-Huang Yu, Argy Cheng, Jonathan Chou, Chuan-Jen Chang, Joseph Ku, Tzong-Lin Wu, and Ruey-Beei Wu, “Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Co-Analysis,” IEEE Transactions on Electromagnetic Compatibility, Apr. 2010
  14. Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, and Hsin-Shu Chen, “A 1-GS/s 6-bit Two-Channel Two-Step ADC in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 3051-3059, Nov. 2009
  15. Li-Yuan Yang, Hsin-Shu Chen, and Yi-Jan Emery Chen, “A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier,” IEEE Microwave and Wireless Components Letters, Vol. 18, No. 3, pp. 197-199, Mar. 2008
  16. Hsin-Shu Chen, Bang-Sup Song and Kantilal Bacrania, “A 14b 20MSamples/s CMOS Pipelined ADC,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp. 997-1001, Jun. 2001

Conference & proceeding papers:

  1. Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, and Shi-Wei Wu, “A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration,” IEEE ISCAS, Seville, Spain, Oct. 2020
  2. Hsin-Shu Chen, Chien-Jian Tseng, Cheng-Ming Chen, Hsiang-Wen Chen and Hamed Alsuraisry, “A 34.3dB SNDR, 2.3GS/s, Sub-Radix Pipeline ADC Using Incomplete Settling Technique With Background Radix Detector,,” Institute of Electrical Engineers of Japan (IEEJ) International Conference on Analog VLSI Circuits, Yilan, Taiwan, Oct. 2019
  3. Hsin-Shu Chen, Chien-Jian Tseng, Yu-Wei Chuan, Chun-Wei Chang, Abdulelah Alshehri, Mazen Almalki and Abdulhamid Sayed, “A 10-bit 300 MS/s Pipeline ADC With Time Domain MDAC,,” Institute of Electrical Engineers of Japan (IEEJ) International Conference on Analog VLSI Circuits, Yilan, Taiwan, Oct. 2019
  4. Chi-Wei Chen, Hsin-Shu Chen and Wen-Jong Wu, “A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique,” IEEE MWSCAS, pp. 806-809, Dallas, TX, USA, Aug. 2019
  5. Yao-Sheng Hu, Li-Yu Huang, and Hsin-Shu Chen, “A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 103-106, Tainan, Taiwan, Nov. 2018
  6. Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, and Hsin-Shu Chen, “An 89.55dB-SFDR 179.6dB-FoMS 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 253-256, Tainan, Taiwan, Nov. 2018
  7. Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart, and Wen-Jong Wu, “A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting,” IEEE ISCAS, pp. 1-4, Florence, Italy, May 2018
  8. Yao-Sheng Hu, Kai-Yue Lin and Hsin-Shu Chen, “A 510nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-Switching Technique,” IEEE Dig. Symp. VLSI Circuits, pp. C238-C239, Kyoto, Japan, Jun. 2017
  9. Hsin-Shu Chen, Jia-Nan Tai, Jau-Horng Chen, and Yi-Jan Emery Chen, “A Current Average Control Method for Transient-Glitch Reduction in Variable Frequency DC-DC Converters,” IEEE ISCAS, pp.1290-1293, Baltimore, MD, USA, May 2017
  10. Yu-Chieh Hsieh, Jiun-Jung Chen, Hsin-Shu Chen, and Wen-Jong Wu, “An Integrated Circuit Design of High Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting,” PowerMEMS, pp. 1-5, Paris, France, Dec. 2016
  11. Yao-Sheng Hu, Kai-Yue Lin, and Hsin-Shu Chen, “A 12-bit 200kS/s Subranging SAR ADC with an Energy-Curve Reshape Technique,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 149-152, Toyama, Japan, Nov. 2016
  12. Yao-Sheng Hu, Po-Chao Huang, Mi-Di Yang, Shi-Wei Wu, and Hsin-Shu Chen, “A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s Two-Step SAR ADC,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 81-84, Toyama, Japan, Nov. 2016
  13. Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, and Hsin-Shu Chen, “An 8-bit 900MS/s Two-Step SAR ADC,” IEEE ISCAS, pp. 2898-2898, Montreal, Canada, May 2016
  14. Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 81-84, Kaohsiung, Taiwan, Nov. 2014
  15. Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, and Hsin-Shu Chen, “A 0.85fJ/conversion-step 10-bit 200kS/s subranging SAR ADC in 40nm CMOS,” IEEE International Solid-State Circuits Conf. Dig. Tech. Papers, pp. 196-197, San Francisco, CA, USA, Feb. 2014
  16. Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, and Hsin-Shu Chen, “A 0.004mm2 Single-Channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 277-280, Singapore, Nov. 2013
  17. Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” IEEE Dig. Symp. VLSI Circuits, pp. 92-93, Honolulu, Hawaii, USA, Jun. 2012
  18. Jia-Nan Tai, Hsin-Shu Chen and Hang-Quei Chiu, “A Highly Integrated Class-D Amplifier using Driver Delay Hysteresis Control,” IEEE VLSI-DAT, pp. 1-4, Hsinchu, Taiwan, Apr. 2012
  19. Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, and Hsin-Shu Chen, “A 10b 320MS/s Self-Calibrated Pipeline ADC,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 173-176, Beijing, China, Nov. 2010
  20. Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, and Hsin-Shu Chen, “A 3mW 12b 10MS/s Sub-Range SAR ADC,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 153-156, Taipei, Taiwan, Nov. 2009
  21. Yu-Hsiang Lin, Jonathan Chou, Yi-Chang Lu, Tzong-Lin Wu, and Hsin-Shu Chen, “Chip-Package-Board Co-design – a DDR3 System Design Example from Circuit Designers’ Perspective,” IEEE EDAPS, pp. 27-30, Seoul, Korea, Dec. 2008
  22. Hsin-Shu Chen and Chao-Ching Hung, “A Self-Calibrated Multiphase DLL-Based Clock Generator,” IEEE VLSI-DAT, pp. 1-4, Hsinchu, Taiwan, Apr. 2007
  23. Chien-Kai Hung, Jian-Feng Shiu, I-Ching Chen and Hsin-Shu Chen, “A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp. 335-338, Hangzhou, China, Nov. 2006
  24. Sen-Wen Hsiao, Yen-Chih Huang, David Liang, Hung-Wei Kevin Chen and Hsin-Shu Chen, “A 1.5-V 10-ppm/ºC 2nd-Order Curvature-Compensated CMOS Bandgap Reference with Trimming,” IEEE ISCAS, pp.565-568, Kos, Greece, May 2006
  25. Tang-Nian Luo, Shuen-Yin Bai, Yi-Jan Emery Chen, Hsin-Shu Chen and Deukhyoun Heo, “A 1-V CMOS VCO For 60-GHz Applications,” Asia-Pacific Microwave Conference, Suzhou, China, Dec. 2005
  26. Hsin-Shu Chen, Bang-Sup Song and Kantilal Bacrania, “A 14b 20MSamples/s CMOS Pipelined ADC,” IEEE International Solid-State Circuits Conf. Dig. Tech. Papers, pp. 46-47, San Francisco, CA, USA, Feb. 2000
  27. Hsin-Shu Chen and Akira Ito, “Characterization of 1/f noise vs. number of gate stripes in MOS transistors,” IEEE ISCAS, pp. II310-II313, Orlando, FL, USA, May 1999

Patents:

  1. 曾千鑑和陳信樹, “管線式類比數位轉換方法及其裝置,” 台灣 發明第I548223號, Sept. 2016
  2. 戴宏彥和陳信樹, “類比數位轉換電路及其轉換方法,” 台灣發明第I542158號, Jul. 2016
  3. 戴宏彥、胡耀升和陳信樹, “類比數位轉換裝置及其轉換方法,” 台灣發明第I532328號, May 2016
  4. 戴宏彥和陳信樹, “類比數位轉換裝置,” 台灣發明第I523435號, Feb. 2016
  5. Hung-Yen Tai, Yao-Sheng Hu, and Hsin-Shu Chen, “Analog to Digital Conversion Device and Analog to Digital Conversion Method,” U.S. Patent No: US9,143,153 B1, Sept. 2015
  6. 劉邦榮和陳信樹, “電源轉換器舆控制方法,” 台灣發明第I499188號, Sept. 2015
  7. 戴宏彥、陳宏維和陳信樹, “連續近似式類比至數位轉換器,” 台灣發明第I492547號, Jul. 2015
  8. 陳信樹, “校正增益誤差的自校正系統及其自校正方法,” 台灣發明第I445318號, Jul. 2014
  9. Hung-Yen Tai, Hung-Wei Chen, and Hsin-Shu Chen, “Successive Approximation Analog-To-Digital Converter,,” U.S. Patent No.: US8,742,971 B1, Jun. 2014
  10. 陳宏維和陳信樹, “具自時脈的類比數位轉換裝置及其方法,” 台灣發明第I426711號, Feb. 2014
  11. 陳宏維和陳信樹, “次區間的類比數位轉換裝置及其方法,” 台灣發明第I407702號, Sept. 2013
  12. 洪健凱和陳信樹, “放大器陣列電路及快閃式類比數位轉換器,” 台灣發明第I335140號, Dec. 2010
  13. Chien-Kai Hung, and Hsin-Shu Chen, “Amplifier Array Circuits and Flash Analog to Digital Converters,” U.S. Patent No.: US 7,554,477 B2, Jun. 2009
  14. Hsin-Shu Chen, et al., “Track and Hold with Dual Pump Circuit,” U.S. Patent No.: US6,731,155 B2, May 2004
  15. Hsin-Shu Chen, et al., “System and Method of DC Calibration of Amplifiers,” U.S. Patent No.: US 6,714,886 B2, Mar. 2004
  16. Hsin-Shu Chen, et al., “Calibration of Resistor Ladder Using Difference Measurement and Parallel Resistive Correction,” U.S. Patent No.: US6,628,216 B2, Sept. 2003
  17. Hsin-Shu Chen, et al., “An Analog to Digital Converter Using Subranging and Interpolation,” U.S. Patent No.: US6,570,523 B1, May 2003

other:

  1. 陳信樹, “高效能電路系統,” Dec. 2014, 工程科技通訊143期,pp25-26
  2. 戴嘉南和陳信樹, “使用展頻技巧的脈衝寬度調變直流電壓轉換器,” Dec. 2010, 零組件雜誌,卷期230,pp104-105
  3. 陳信樹, “子計畫五:運用於60GHz寬頻無線通訊系統之高速類比數位轉換器(3/3),” Aug. 2010, 工程科技通訊107期,pp188-192
  4. 陳信樹, “數位延遲鎖相迴路介紹,” Apr. 2007, 零組件雜誌,卷期186,pp74-78
  5. 鍾政峰和陳信樹, “高速數位類比轉換器操作原理及設計考量,” Jan. 2005, 新電子雜誌
  6. 杜明哲和陳信樹, “混合訊號電路元件—取樣電路的設計原理與挑戰,” Feb. 2004, 新電子雜誌