李建模教授的著作列表 - Publication List of Chien-Mo Li

Publication List of 李建模 Chien-Mo (James) Li

Journal articles & book chapters:

  1. Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai Tsai-Chieh Chen and James Chien-Mo Li, “DR-scan: Dual-rail Asynchronous Scan DfT and ATPG,” IEEE Trans. CAD, 2018
  2. B. Liu, J. C.M. Li,, “PSN-aware Circuit Test Timing Prediction using Machine Learning,” IET Computers & Digital Techniques, vol. 11, no. 2, pp. 60-67, 3 2017., 2017
  3. W. E. Wei, H. Y. Li, C. Y. Han, J. C. M. Li, J. J. Huang, I. C. Cheng, C. N. Liu, and Y. H. Yeh, “A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects,” IEEE Journal of Display Technology, Dec. 2014
  4. Y. L. Chen ; W. R. Wu ; C. N. J. Liu ; J. C. M. Li, “Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics,” IEEE Trans. Computer-aided Design of IC and Syst, 2014
  5. C.Y. Kuo, C. J. Shih, J. C. M. Li, K. Chakrabarty, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,” IEEE Trans. VLSI Sys., 2014
  6. E. H. Ma, W. E. Wei, H. Y. Li, J. C. M. Li, I. C. Cheng, and Y. H. Yeh, “Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects,” IEEE Journal of Display Technology, 2014
  7. P. J. Chen , C. C. Che, J. C. M. Li, S. F. Kuo, P. Y. Hsueh, C. Y. Kuo and J. N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,” IET Proceedings Computers and Digital Techniques, 2014
  8. J. Y. Chang, K. Y. Liao, S. C. Hsu, J. C. M. Li, and J. C. Rau, “Compact Test Pattern Selection for Small Delay Defect,” IEEE Trans. Computer-aided Design of IC and Syst, May 2013
  9. Y. C. Huang, M. H. Tsai, W. S. Ding, J. C. M. Li, M. T. Chang, M. H. Tsai, C. M. Tseng and H. C. Li, “Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering,” IEEE Trans. Computer-aided Design of IC and Syst, 2013
  10. C. J. Shih, C. Y. Hsu, C. Y. Kou, J. C. M. Li, J. C. Rau and K. Chakrabarty,, “Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC,” Active and Passive Electronic Components, Hindawi publishing, 2012
  11. S. Wu, L. T. Wang, X. Wen, W. B. Jone, M. S. Hsiao, F. Li, J. C. M. Li, J. L. Huang,, “Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,,” ACM Transactions on Design Automation of Electronic Systems (TODAES),, 2012
  12. Y. S. Wang, M. H. Hsieh, J. C. M. Li, and C. C. P. Chen, “An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example,” IEEE Trans. on Circuits and systems I, 2012
  13. G.M. Chiu and J. C. M. Li, “A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores,” IEEE Trans. VLSI Systems, VOL. 20, NO. 1, JANUARY, pp. 126-134, 2012
  14. W.L. Tsai, J. C.M. Li, “Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis,” IEEE Trans. Comput, 2012
  15. W.C. Wang and J.C.M Li, “Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips,” IET Computers & Digital Techniques, 2011
  16. C. H. Cheng, and J. C. M. Li, “An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology,” Journal of Electronic Testing, Volume 27, Issue 2 (2011), Page 193, 2011
  17. Liao, “A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives,” IEEE Trans. Computer-aided Design of IC and Syst, Vol. 30, No.11, pp.1767-1772, 2011
  18. C. Liu, E. Ma and J. C.M. Li, “Placement Optimization of Flexible TFT Digital Circuits,” IEEE Design & Test of Computers, Vol. 28, NO. 6, pp.24-31, 2011, 2011
  19. W.-C. Kao, W.-S. Chuang, H.-T. Lin, J. C.-M. Li, and V, Manquinho, “DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in,” IEEE Trans. on VLSI Systems, Vol 18, No.3, 2010
  20. Shiue-Tsung Shen, Chester Liu, En-Hua Ma, I-Chun Cheng, and James Chien-Mo Li, “Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and IDDQ Testing,” Journal of Display Technology, Vol. 6, Issue 12, 2010
  21. F. M. Wang, W.-C. Wang , and J. C-M. Li, “Time-space test response compaction and diagnosis based on BCH codes,” IET Computers & Digital Techniques, Volume 3, Issue 3, p. 304-313, May 2009
  22. J. C.-M. Li, P.-C. Lin, P.-C. Chiang, C.-M. Pan and C.W. Tseng, “Effective and Economic Phase Noise Testing for Single-Chip TV Tuners,” IEEE Trans. on Instrumentation and Measurement, Vol.57, No. 10, pp2265-2272, 2008
  23. Y. Huang, R Guo, W.T. Cheng, and J. C.-M. Li,, “Survey of Scan Chain Diagnosis,” IEEE Design & Test of Computers,, Vol. 25, NO. 3, pp.240-248,, 2008
  24. W.S. Chuang, James C.-M. Li, “Diagnosis of Multiple Scan Chain Timing Faults,” IEEE Trans. Computer-aided Design of IC and Syst., Vol. 27, No.6, pp.1104-1116, 2008
  25. H.T. Lin and J. C.M. Li, “Simultaneous capture and shift power reduction test pattern generator for scan testing,” IET Computers & Digital Techniques,, Volume: 2, No. 2 pp.: 132-141, March, 2008
  26. Chun-Yi Lee, James C.-M. Li, “Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing,” Journal of Low Power Electronic, Vol. 3, NO.2, 206-216, Aug. 2007
  27. J. C.-M. Li, Hung-Mao Lin and Fang Min Wang, “Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis,” IEEE Trans. Computers, Vol56, NO3, 402-414, Mar. 2007
  28. Li, J. C.-M. and E. J. McCluskey, “Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC,” IEEE Trans. on Computer-Aided Design, Nov. 2005
  29. Li, J. C. M., “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, 54, 1467-1472, Nov. 2005
  30. Li, J. C.-M., “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains,” IEEE Trans. on VLSI Systems, Vol.13, No. 6, Jun. 2005
  31. Li, J. C.-M., “Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol. E88-A, No.4, pp. 1024-1030, Apr. 2005
  32. Li, J. C. M., “A Design for Testability Technique for Low Power Delay Fault Testing,” IEICE Trans. on Electronics, Apr. 2004

Conference & proceeding papers:

  1. Shih-An. Hsieh, Y.-H.Wang, K.Y. Huang, and James C.M Li, “DR Scan: DR-scan: A Test Methodology for Dual-rail Asynchronous Circuit,” Design Automation Conference, poster, 2015
  2. A.F. Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li, “TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal Defects,” IEEE VLSI/DAT, 2015
  3. B.C. Bai, C.A. Chen, J C.M Li, “Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing,” IEEE International Test Conference, poster, 2014
  4. SM Chao, PJ Chen, JCM Li, and et. al, “Divide and Conquer Diagnosis for Multiple Defects,” IEEE International Test Conference, 2014
  5. H.Y. Hsieh, J. C.-M. Li, “Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D IC,” IEEE 3D IC Test Workshop, 2014
  6. H.Y. Lee, C.Y. Han, J. C.-M. Li, “GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse,” IEEE/ACM Design Automation Conference, poster, 2014
  7. K.Y. Liao, J. C.-M. Li, M. Hsiao, “GPU-Based Timing-Aware Test Generation for Small Delay Defects,” IEEE European Test Symposium, poster, 2014
  8. SC Hsu, KY Liao, JCM Li, “Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPU,” VLSI/CAD, 2013
  9. KY Liao, SC Hsu, and JCM Li, “GPU-Based N-Detect Transition Fault ATPG,” Proc. IEEE/ACM Design Automation Conf., 2013
  10. WS Ding, HY Hsieh, and JCM Li, “Test Pattern Modification for Average IR-drop Reduction,” IEEE Int’l Test Conf., poster, 2013
  11. Bing-Chuan Bai, Chen-An Chen, Yee-Wen Chen, Ming-Hsueh Wu, Kun-Lun Luo, Chun-Lung Hsu, Liang-Chia Cheng, and Chien-Mo Li, “Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAM,” IEEE Int’l Test Conf., poster, 2013
  12. Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong Roland Jiang and Chien-Mo Li, “Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions,” Proc. Int’l Conf. on CAD, 2013
  13. Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, and K. Chakrabarty, “Testing Leakage Faults of Power TSV in 3D IC,” IEEE Int’l workshop on 3D IC, 2013
  14. BC Bai, C-L Hsu, MH Wu, CA Chen, YW Chen, KL Luo, LC Cheng, JCM Li, “Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM,” IEEE Asian Test Symposium, 2013
  15. Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, and K. Chakrabarty, “Test Generation of Path Delay Faults Induced by Defects in Power TSV,” IEEE Asian Test Symposium, 2013
  16. MH Tsai, WS Ting, JCM Li, “Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,” VTTW, 2012
  17. EH Ma, WE Wei, JCM Li, “Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects,” VLSI/CAD, 2012
  18. CY Hsu, CY Kuo, JCM Li, K. Chakrbarty, “3D IC test scheduling using simulated annealing,” IEEE VLSI-DAT, 2012
  19. KY Liao, SC Hsu, JCM Li, “GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,” IEEE Int’l Test Conf., poster, 2012
  20. C.Y. Kuo, C. J Shih, JCM Li, K. Chakrabarty, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,” IEEE 3D IC Test workshop, 2012
  21. M. H. Tsai, W. S. Ting, J. C. M. Li,, “Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,,” ITC, poster, 2012
  22. K. Y. Liao, S. C. Hsu, J. C. M. Li,, “GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,,” ITC, poster, 2012
  23. B. C. Bai, J. C. M. Li,, “Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs,” ITC, poster, 2012
  24. C.Y. Kuo, C. J. Shih, J. C. M. Li, K. Chakrabarty,, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,,” IEEE 3D IC Test workshop, 2012
  25. P. J. Chen, C. C. Che, J. C. M. Li and K. Y. Tsai, S. F. Kuo, P. Y. Hsueh, Y. Y. Chen and J. N. Lee,, “Systematic Open Via Diagnosis Based on Physical Features,” IEEE Silicon Debug and Diagnosis Workshop, 2012
  26. R.Y. Wen, Y.C. Huang, M.H. Tsai, K.Y. Liao, J. C.-M. Li, M.-T. Chang, M.-H. Tsai, C.-M. Tseng and H.-C. Li, “Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan,” Proc. IEEE Int’l Test Conf., paper 12.1, 2011
  27. Y. Wang, M. Hsieh, C. Liu, C. Liu, J. C.-M. Li, and C.-P. Chen, “An At-speed Self-testable Technique for the High Speed Domino Adder,” Proc. IEEE CICC poster, 2011
  28. CY Hsu, JCM Li, K. Chakrbarty, “Thermal-aware Test scheduling for 3D ICs,” IEEE Int’l 3D IC Test Workshop, 2011
  29. B. R. Chen and J. CM Li, “An Accurate Timing-aware Diagnosis Algorithm for Multiple Small Delay Defects,” VTTW, 2011
  30. CY Chang, K.Y, Liao and J.CM Li, “Compact test pattern Selection for Small Delay Defects,” VLSI/CAD, 2011
  31. B. R. Chen, JCM Li, and et. al., “An Accurate Timing-aware Diagnosis Algorithm for Multiple Small Delay Defects,” Proc. IEEE Asian Test Symposium, 2011
  32. Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.;, “Static timing analysis for flexible TFT circuits,” Design Automation Conference (DAC), Jun. 2010
  33. Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M., “CSER: BISER-based concurrent soft-error resilience,” VLSI Test Symposium (VTS), Apr. 2010
  34. WC Wang and JCM Li, “Row-LFSR-Column (RLC) Test Response Masking Technique,” VLSI/CAD, 2010
  35. Wei-Che Wang and James C.-M. Lim Yi-Chih Sung, Amy Rao, and Laung-Terng Wang, “Test Response Compaction in the Presence of Many Unknowns,” VTTW, 2009
  36. Shang-Feng Chao, Jheng-Yang Ciou, and James Chien-Mo Li, “Transition Fault Diagnosis Using At-speed Test Patterns,” IEEE Int’l Workshop on RTL and High Level Testing, paper 5.3, 2009
  37. B. R. Chen and J. C.M. Li, “Bridging Fault Diagnosis to Identify the Layer of Systematic Defects,” Proc. IEEE Asian Test Symposium, paper 8B.2, 2009
  38. Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, J. C.-M. Li, I-Chun Cheng, “Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits,” Proc. IEEE Asian Test Symposium, paper 3C.4, 2009
  39. T.-F. Chien, W.-C. Chao, J. C.-M. Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “BIST Design Optimization for Large-Scale Embedded Memory Cores,” Proc. Int’l Conf. on Computer-Aided Design, 2009
  40. B. C. Bai, “Power Scan: DFT for Power Switches in VLSI Designs,” Proc. IEEE Int’l Test Conf., poster #7, 2009
  41. S.T. Shen, W. H. Liu, J. C. M Li, and I-Chun-Cheng, “Very-low Voltage Testing of TFT Circuits,” Proc. IEEE Int’l Test Conf., poster, 2009
  42. B. C. Bai, A. K Li, J. C.M. Li, and K. C. Wu, “Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs,” Proc. IEEE ASP-DAC, 2009
  43. Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li, “Diagnosis of Logic-chain Bridging Faults,” IEEE Int’l Workshop on RTL and High Level Testing, 2009
  44. T.-F. Chien, W.-C. Chao, J. C.-M. Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “BIST Design Optimization for Large-Scale Embedded Memory Cores,” Proc. Int’l Conf. on Computer-Aided Design, 2009
  45. G-M. Chiu and J. Li, “IEEE 1500-compatible Secure Test Wrapper for Embedded IP Cores,” IEEE Int’l Test Conf., PO#4, 2008
  46. Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chih-Mou Tseng, “Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise,,” Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, PO#22, 2008
  47. W-C. Liu, J. Li, W-L. Tsai, H-T. Lin,, “Diagnosis of Logic-to-Chain Bridging Faults,” IEEE Int’l Test Conf., PO#16, 2008
  48. Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte, “On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs,” IEEE Int’l Symp. Proc. Defect and Fault Tolerant in VLSI Systems, 2008
  49. P.-C. Lin, C.-H. Hsu, J. C.-M. Li, C.-M. Chiang, and C.-J. Pan,, “Phase Noise Testing of Single Chip TV Tuners,,” IEEE VLSI-DAT, 2008
  50. C. H. Cheng, C.-H. Hsu , and J. C.M. Li, “An Asynchronous DFT Technique for TFT Macroelectronics,” International Symposium on Flexible Electronics and Display (ISFED), paper 4-6, 2008
  51. Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li, “Diagnosis of Logic-chain Bridging Faults,” IEEE Int’l Workshop on RTL and High Level Testing, paper 5.3, 2008
  52. C. H. Cheng, J. C.M. Li, “A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT Technology,” VLSI/CAD, 2008
  53. Shang-Feng Chao and J. C.-M. Li, “Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks,” VLSI/CAD, 2008
  54. Geng-Ming Chiu, C.-Y. Chiu, R-Y. Wen, and James Chien-Mo Li, “IEEE [1500 Compatible Secure Test Wrapper For Embedded IP Cores,” VTTW, 2008
  55. C.Y. Lee, H.M. Lin, F.M. Wang, and J. C. M. Li, “Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies,” IEEE Asian South Pacific Design Automation Conference (ASP-DAC), Jan. 2007
  56. B.-H. Chen, Wei-Chuang Kao, Bin-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li, “Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique,” IEEE Asian Test Symposium, 2007
  57. Y. L Kao, W. S. Chuang, and J. C. M Li, “Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique,” IEEE Int'l Test Conf., Santa Clara, Oct. 2006
  58. Yu-Long Kao, Wei-Shun Chuang and J. C.-M. Li, “Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique,” VLSI/CAD, 2006
  59. Bo-Hua Chen and J. C.-M. Li, “CRC BIST: A Low Peak Power Self Technique,” VLSI/CAD, 2006
  60. H.M. Lin and J. C. M. Li, “Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains,” Proc. IEEE Int’l Test Conf., paper 42.3, Oct. 2005
  61. M.H. Chiu and J. C. M Li, “Jump Scan: A DFT Technique for Low Power Testing,,” Proc. IEEE VLSI Test Symposium, pp. 277-282, May 2005
  62. Lee, C-Y and Li, C-M, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” Asia Solid-State Circuit Conference (ASSCC), Taiwan, 2005
  63. C.Y. Lee and J. C. M. Li, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” IEEE Asian Solid State Circuit Conf., 2005
  64. P.C. Lin, J. C.-M. Li, Chih-Ming Chiang, and Chuo-Jan Pan, “Effective and Economic Phase Noise Testing for Single Chip TV Tuners,” VLSI/CAD Symposium, 2005
  65. Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique,” VLSI/CAD Symposium, 2005
  66. Yu-Te Liaw and James C.-M. Li, “A Two-level Test Data Compression and Test Time Reduction Technique for SOC,” VLSI/CAD Symposium, 2005
  67. E. J. McCluskey, A. Alyamani, J. C. M. Li, C. W. Tseng, E. Volkerink, F. F. Feriani, E. Li and S. Mitra, “ELF-Murphy Data on Defects and Test Sets,” Proc. IEEE VLSI Test Symposium, pp. 16-22, 2004
  68. L. W. Ko and C.M. Li, “Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique,” VLSI/CAD Symposium, pp.55, 2004
  69. C. K. Yo and C.M. Li, “Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation Patterns,” VLSI/CAD Symposium, pp.94, 2004
  70. Li, J. C.M. and E. J. McCluskey, “Diagnosis for Sequence Dependent Chips,” Proc. IEEE VLSI Test Symposium, pp.187-192, 2002
  71. C.W.Tseng, J.C.M. Li and E. J. McCluskey, “Experimental Results for Slow Speed Testing,” IEEE VLSI Test Symposium, 2002
  72. Mitra, S., C.W. Tseng, J. C. M Li, and E. J. McCluskey, “Pseudo Random Testing Theoretical Models vs. Real Data,” IEEE International Workshop on Test Resource Partitioning, 2001
  73. Li, J. C.M., Tseng, C.W. and E.J. McCluskey, “Testing for Resistive and Stuck Opens,” Proc. International Test Conference, pp. 1049-1058, 2001
  74. Li, J. C.M. and E.J. McCluskey, “Diagnosis of Tunneling Opens,” Proc. IEEE VLSI Test Symposium, pp.22-27, 2001
  75. Li, J. C.M and E.J. McCluskey, “Testing for Tunneling Opens,” Proc. International Test Conference, pp. 85-94, 2000

Books:

  1. J. C.-M. Li, and M. Hsiao, “Electronic Design Automation,” Morgan Kaufmann, 2009
  2. Wang, Wu, Wen and et. al., “VLSI Test Principles and Architectures,” Morgan Kaufmann, USA, 800 pages, 2006, ISBN:ISBN-10: 0123705975 and ISBN-13: 978-0123705976

Patents:

  1. J. Y. Wen and J. C. M. Li, “Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium,” 美國/中華民國專利申請中, 2010
  2. 王偉哲 李建模, “包含未知訊號之測試結果壓縮設計,” 中華民國專利申請中, 2009
  3. 鄭啟玄 李建模, “非同步電路可測試設計,” 中華民國專利 (專利號I 403745), Aug. 2008
  4. 邱銘豪 李建模, “跳躍式掃描: 低功率可測試設計,” 中華民國專利 (專利號265293), Dec. 2006