李建模教授的著作列表 - Publication List of Chien-Mo Li

Publication List of 李建模 Chien-Mo (James) Li

Journal articles & book chapters:

  1. Tsai-Chieh Chen,·Chia-Cheng Pai,·Yi-Zhan Hsieh,·Hsiao-Yin Tseng,·James Chien-Mo Li,·Tsung-Te Liu,·I-WeiChiu, “Clock-less DFT and BISTfor Dual-rail Asynchronous Circuits,” Journal of Electronic Testing: Theory and Application, 2021
  2. Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai Tsai-Chieh Chen and James Chien-Mo Li, “DR-scan: Dual-rail Asynchronous Scan DfT and ATPG,” IEEE Trans. CAD, 2018
  3. B. Liu, J. C.M. Li,, “PSN-aware Circuit Test Timing Prediction using Machine Learning,” IET Computers & Digital Techniques, vol. 11, no. 2, pp. 60-67, 3 2017., 2017
  4. CY Chen, YC Lee, CM Li,, “Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration,,” IEICE Trans on Electronics, 2016
  5. HI Lee, CY Han, JCM Li, , “A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse,,” IEEE Tran. On Comput. Aided Design,, 2016
  6. WS Ding, HY Hsieh, CY Han, JCM Li,, “Test Pattern Modification for Average IR-Drop Reduction,,” IEEE TVLSI,, 2016
  7. H. Y. Lee, C. Y. Han, J. C. M Li,, “A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse,,” IEEE Trans. CAD,, 2016
  8. MH Tsai, W-S Ding, HY Hsieh, and J. C.-M. Li, , “Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,” IEEE Trans. VLSI Sys., 2016
  9. W. E. Wei, H. Y. Li, C. Y. Han, J. C. M. Li, J. J. Huang, I. C. Cheng, C. N. Liu, and Y. H. Yeh, “A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects,” IEEE Journal of Display Technology, Dec. 2014
  10. Y. L. Chen ; W. R. Wu ; C. N. J. Liu ; J. C. M. Li, “Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics,” IEEE Trans. Computer-aided Design of IC and Syst, 2014
  11. C.Y. Kuo, C. J. Shih, J. C. M. Li, K. Chakrabarty, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,” IEEE Trans. VLSI Sys., 2014
  12. E. H. Ma, W. E. Wei, H. Y. Li, J. C. M. Li, I. C. Cheng, and Y. H. Yeh, “Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects,” IEEE Journal of Display Technology, 2014
  13. P. J. Chen , C. C. Che, J. C. M. Li, S. F. Kuo, P. Y. Hsueh, C. Y. Kuo and J. N. Lee, “Physical-aware Systematic Multiple Defect Diagnosis,” IET Proceedings Computers and Digital Techniques, 2014
  14. J. Y. Chang, K. Y. Liao, S. C. Hsu, J. C. M. Li, and J. C. Rau, “Compact Test Pattern Selection for Small Delay Defect,” IEEE Trans. Computer-aided Design of IC and Syst, May 2013
  15. Y. C. Huang, M. H. Tsai, W. S. Ding, J. C. M. Li, M. T. Chang, M. H. Tsai, C. M. Tseng and H. C. Li, “Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering,” IEEE Trans. Computer-aided Design of IC and Syst, 2013
  16. C. J. Shih, C. Y. Hsu, C. Y. Kou, J. C. M. Li, J. C. Rau and K. Chakrabarty,, “Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC,” Active and Passive Electronic Components, Hindawi publishing, 2012
  17. S. Wu, L. T. Wang, X. Wen, W. B. Jone, M. S. Hsiao, F. Li, J. C. M. Li, J. L. Huang,, “Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,,” ACM Transactions on Design Automation of Electronic Systems (TODAES),, 2012
  18. Y. S. Wang, M. H. Hsieh, J. C. M. Li, and C. C. P. Chen, “An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example,” IEEE Trans. on Circuits and systems I, 2012
  19. G.M. Chiu and J. C. M. Li, “A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores,” IEEE Trans. VLSI Systems, VOL. 20, NO. 1, JANUARY, pp. 126-134, 2012
  20. W.L. Tsai, J. C.M. Li, “Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis,” IEEE Trans. Comput, 2012
  21. W.C. Wang and J.C.M Li, “Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips,” IET Computers & Digital Techniques, 2011
  22. C. H. Cheng, and J. C. M. Li, “An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology,” Journal of Electronic Testing, Volume 27, Issue 2 (2011), Page 193, 2011
  23. Liao, “A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives,” IEEE Trans. Computer-aided Design of IC and Syst, Vol. 30, No.11, pp.1767-1772, 2011
  24. C. Liu, E. Ma and J. C.M. Li, “Placement Optimization of Flexible TFT Digital Circuits,” IEEE Design & Test of Computers, Vol. 28, NO. 6, pp.24-31, 2011, 2011
  25. W.-C. Kao, W.-S. Chuang, H.-T. Lin, J. C.-M. Li, and V, Manquinho, “DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in,” IEEE Trans. on VLSI Systems, Vol 18, No.3, 2010
  26. Shiue-Tsung Shen, Chester Liu, En-Hua Ma, I-Chun Cheng, and James Chien-Mo Li, “Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and IDDQ Testing,” Journal of Display Technology, Vol. 6, Issue 12, 2010
  27. F. M. Wang, W.-C. Wang , and J. C-M. Li, “Time-space test response compaction and diagnosis based on BCH codes,” IET Computers & Digital Techniques, Volume 3, Issue 3, p. 304-313, May 2009
  28. J. C.-M. Li, P.-C. Lin, P.-C. Chiang, C.-M. Pan and C.W. Tseng, “Effective and Economic Phase Noise Testing for Single-Chip TV Tuners,” IEEE Trans. on Instrumentation and Measurement, Vol.57, No. 10, pp2265-2272, 2008
  29. Y. Huang, R Guo, W.T. Cheng, and J. C.-M. Li,, “Survey of Scan Chain Diagnosis,” IEEE Design & Test of Computers,, Vol. 25, NO. 3, pp.240-248,, 2008
  30. W.S. Chuang, James C.-M. Li, “Diagnosis of Multiple Scan Chain Timing Faults,” IEEE Trans. Computer-aided Design of IC and Syst., Vol. 27, No.6, pp.1104-1116, 2008
  31. H.T. Lin and J. C.M. Li, “Simultaneous capture and shift power reduction test pattern generator for scan testing,” IET Computers & Digital Techniques,, Volume: 2, No. 2 pp.: 132-141, March, 2008
  32. Chun-Yi Lee, James C.-M. Li, “Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing,” Journal of Low Power Electronic, Vol. 3, NO.2, 206-216, Aug. 2007
  33. J. C.-M. Li, Hung-Mao Lin and Fang Min Wang, “Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis,” IEEE Trans. Computers, Vol56, NO3, 402-414, Mar. 2007
  34. Li, J. C.-M. and E. J. McCluskey, “Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC,” IEEE Trans. on Computer-Aided Design, Nov. 2005
  35. Li, J. C. M., “Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains,” IEEE Trans. on Computers, 54, 1467-1472, Nov. 2005
  36. Li, J. C.-M., “Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains,” IEEE Trans. on VLSI Systems, Vol.13, No. 6, Jun. 2005
  37. Li, J. C.-M., “Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, Vol. E88-A, No.4, pp. 1024-1030, Apr. 2005
  38. Li, J. C. M., “A Design for Testability Technique for Low Power Delay Fault Testing,” IEICE Trans. on Electronics, Apr. 2004

Conference & proceeding papers:

  1. Min-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo Li, Eric Fang,, “Chip Performance Prediction Using Machine Learning Techniques,,” VLSI-DAT , 2021
  2. Hsiao-Yin Tseng, I-Wei Chiu, Mu-Ting Wu, and James Chien-Mo Li,, “Machine Learning-Based Test Pattern Generation for Neuromorphic Chips,,” IEEE ICCAD, 2021
  3. Mu-Ting Wu, Cheng-Sian Kuo, and James Chien-Mo Li Chris Nigh and Gaurav Bhargava,, “Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization,,” IEEE Int’l Test Conf., 2021
  4. Kuo, Chun Chen, Chao-Ho Hsieh, Wei-Chen Lin, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh,, “Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning,,” IEEE Int’l Test Conf, 2021
  5. Y.A Chen, ST Liu, J. C.M. Li,, “A Compaction-oriented Backtrace Heuristic For Dynamic Test Compaction,,” IEEE Workshop on RTL Testing,, 2020
  6. Cheng Yun Hsieh, Chen Hung Wu, Chia Hsien Huang, His-Sheng Goan, and James Chien Mo Li,, “Realistic Fault Model and Fault Simulation for Quantum Dot Quantum Circuits,,” IEEE/ACM Design Automation Conference, 2020
  7. Chen-Hung Wu, Cheng-Yun Hsieh, Jiun-Yun Li, and James Chien-Mo Li, , “qATG: Automatic Test Generation for Quantum Circuits,,” IEEE Int’l Test Conf,, 2020
  8. Heng-Yi Lin, Yen-Chun Fang, Shi-Tang Liu, Jia-Xian Chen, James Chien-Mo Li, Eric Jia-Wei Fang ,, “Automatic IR-Drop ECO Using Machine Learning,,” IEEE Int’l Test Conf. Asia, , 2020
  9. Ming-Ting Lee, Chen-Hung Wu, Shi-Tang Liu, Cheng-Yun Hsieh and James Chien-Mo Li,, “High Efficiency and Low Overkill Testing for Probabilistic Circuits, ,” IEEE Int’l Test Conf. Asia,, 2020
  10. Yan-Shen You, Chih-Yan Liu, Mu-Ting Wu, Po-Wei Chen, James Chien-Mo Li , , “Diagnosis technique for Clustered Multiple Transition Delay Faults,,” IEEE Int’l Test Conf. Asia,, 2020
  11. Chih-Yan Liu, Mu-Ting Wu and James C.-M. Li, Gaurav Bhargava and Chris Nigh,, “Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips,,” IEEE Asian Test Symposium,, 2020
  12. S.C. Sun, S. T. Tsai, J. CM Li, , “PI-PO-Aware Heuristic for Dynamic Test Compaction,,” IEEE Workshop on RTL Testing,, 2019
  13. K.C. Yang, M.T. Lee, C.H. Wu and J.C.M. Li,, “ATPG and Test Compression for Probabilistic Circuits,” IEEE VLSI-DAT, 2019
  14. Yu-wei Chen and James Chien-Mo Li,, “Parallel Order ATPG for Test Compaction,,” IEEE VLSI-DAT, 2018
  15. Yu-Ching Li, and James Chien-Mo Li,, “Diagnosis of Risky Cells (DRC) Responsible for Power-Supply-Noise Violations,,” IEEE VLSI-DAT, 2018
  16. S.Y. Lin , JCM L, Y.C. Liu,, “IR Drop Prediction of ECO-Revised Circuits Using Machine Learning,” IEEE VLSI Test Symp., 2018
  17. Y. S. Liu, M. T. Lee and J.C.M. Li, , “Multiple-order ATPG for Test Compaction,” IEEE Workshop on RTL and High level Testing (WRTLT), 2018
  18. Yen-Chun Fang, Heng-Yi Lin, Min-Yan Su, Chien-Mo Li, Eric Jia-Wei Fang, , “Machine-learning-based Dynamic IR Drop Prediction for ECO,,” IEEE Int’l Conf. on CAD,, 2018
  19. Ting-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li,, “Test methodology for PCHB/PCFB Asynchronous Circuits,,” IEEE Int’l Test Conf., 2018
  20. Y.H. Ho, Y.W. Chen, C. M. Li,, “Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies,” IEEE VLSI-DAT,, 2017
  21. YW Chen,, “Parallel Order ATPG for Test Compaction,,” IEEE/ACM Design Automation Conf. , 2017
  22. KY Huang, TY Sheng, JCM Li,, “Test Methodology for Dual-rail Asynchronous Circuits,” IEEE/ACM Design Automation Conf., 2017
  23. S.Y. Lin, Y.C. Li, JCM Li,, “IR Drop Prediction of ECO-Revised Circuits Using Machine Learning,” IEEE/ACM Design Automation Conf. , 2017
  24. C.M Chang, K.J. Yang, J.C.M. Li,, “est Pattern Compression for Probabilistic Circuits,,” Asian Test Symp. , 2017
  25. PH Chen, CL Lee, JCM Li,, “Physical-aware Diagnosis of Multiple Interconnect Defects,” ITC-asia,, 2017
  26. YC Wang, JCM Li,, “DFT and ATPG of Two-pattern Tests for Dual-rail Asynchronous Circuits,,” IEEE/ACM Design Automation Conference (Poster),, 2016
  27. Brad YC Liu, James Chien-Mo Li,, “PSN-aware Timing Prediction Using Machine Learning,,” IEEE Workshop on RTL and High level Testing (WRTLT),, 2016
  28. C. Y. Han, J. C.-M. Li,, “Power-Supply-Noise-Aware Dynamic Timing Analyzer for Low Power 3D IC,” IEEE 3D IC Test Workshop,, 2015
  29. Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, James Chien-Mo Li,, “Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits,,” Asian Test Symp.,, 2015
  30. Shih-An. Hsieh, Y.-H.Wang, K.Y. Huang, and James C.M Li, “DR Scan: DR-scan: A Test Methodology for Dual-rail Asynchronous Circuit,” Design Automation Conference, poster, 2015
  31. A.F. Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li, “TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal Defects,” IEEE VLSI/DAT, 2015
  32. B.C. Bai, C.A. Chen, J C.M Li, “Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing,” IEEE International Test Conference, poster, 2014
  33. SM Chao, PJ Chen, JCM Li, and et. al, “Divide and Conquer Diagnosis for Multiple Defects,” IEEE International Test Conference, 2014
  34. H.Y. Hsieh, J. C.-M. Li, “Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D IC,” IEEE 3D IC Test Workshop, 2014
  35. H.Y. Lee, C.Y. Han, J. C.-M. Li, “GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse,” IEEE/ACM Design Automation Conference, poster, 2014
  36. K.Y. Liao, J. C.-M. Li, M. Hsiao, “GPU-Based Timing-Aware Test Generation for Small Delay Defects,” IEEE European Test Symposium, poster, 2014
  37. SC Hsu, KY Liao, JCM Li, “Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPU,” VLSI/CAD, 2013
  38. KY Liao, SC Hsu, and JCM Li, “GPU-Based N-Detect Transition Fault ATPG,” Proc. IEEE/ACM Design Automation Conf., 2013
  39. WS Ding, HY Hsieh, and JCM Li, “Test Pattern Modification for Average IR-drop Reduction,” IEEE Int’l Test Conf., poster, 2013
  40. Bing-Chuan Bai, Chen-An Chen, Yee-Wen Chen, Ming-Hsueh Wu, Kun-Lun Luo, Chun-Lung Hsu, Liang-Chia Cheng, and Chien-Mo Li, “Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAM,” IEEE Int’l Test Conf., poster, 2013
  41. Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong Roland Jiang and Chien-Mo Li, “Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions,” Proc. Int’l Conf. on CAD, 2013
  42. Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, and K. Chakrabarty, “Testing Leakage Faults of Power TSV in 3D IC,” IEEE Int’l workshop on 3D IC, 2013
  43. BC Bai, C-L Hsu, MH Wu, CA Chen, YW Chen, KL Luo, LC Cheng, JCM Li, “Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM,” IEEE Asian Test Symposium, 2013
  44. Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, and K. Chakrabarty, “Test Generation of Path Delay Faults Induced by Defects in Power TSV,” IEEE Asian Test Symposium, 2013
  45. MH Tsai, WS Ting, JCM Li, “Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,” VTTW, 2012
  46. EH Ma, WE Wei, JCM Li, “Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects,” VLSI/CAD, 2012
  47. CY Hsu, CY Kuo, JCM Li, K. Chakrbarty, “3D IC test scheduling using simulated annealing,” IEEE VLSI-DAT, 2012
  48. KY Liao, SC Hsu, JCM Li, “GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,” IEEE Int’l Test Conf., poster, 2012
  49. C.Y. Kuo, C. J Shih, JCM Li, K. Chakrabarty, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,” IEEE 3D IC Test workshop, 2012
  50. M. H. Tsai, W. S. Ting, J. C. M. Li,, “Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,,” ITC, poster, 2012
  51. K. Y. Liao, S. C. Hsu, J. C. M. Li,, “GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,,” ITC, poster, 2012
  52. B. C. Bai, J. C. M. Li,, “Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs,” ITC, poster, 2012
  53. C.Y. Kuo, C. J. Shih, J. C. M. Li, K. Chakrabarty,, “Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,,” IEEE 3D IC Test workshop, 2012
  54. P. J. Chen, C. C. Che, J. C. M. Li and K. Y. Tsai, S. F. Kuo, P. Y. Hsueh, Y. Y. Chen and J. N. Lee,, “Systematic Open Via Diagnosis Based on Physical Features,” IEEE Silicon Debug and Diagnosis Workshop, 2012
  55. R.Y. Wen, Y.C. Huang, M.H. Tsai, K.Y. Liao, J. C.-M. Li, M.-T. Chang, M.-H. Tsai, C.-M. Tseng and H.-C. Li, “Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan,” Proc. IEEE Int’l Test Conf., paper 12.1, 2011
  56. Y. Wang, M. Hsieh, C. Liu, C. Liu, J. C.-M. Li, and C.-P. Chen, “An At-speed Self-testable Technique for the High Speed Domino Adder,” Proc. IEEE CICC poster, 2011
  57. CY Hsu, JCM Li, K. Chakrbarty, “Thermal-aware Test scheduling for 3D ICs,” IEEE Int’l 3D IC Test Workshop, 2011
  58. B. R. Chen and J. CM Li, “An Accurate Timing-aware Diagnosis Algorithm for Multiple Small Delay Defects,” VTTW, 2011
  59. CY Chang, K.Y, Liao and J.CM Li, “Compact test pattern Selection for Small Delay Defects,” VLSI/CAD, 2011
  60. B. R. Chen, JCM Li, and et. al., “An Accurate Timing-aware Diagnosis Algorithm for Multiple Small Delay Defects,” Proc. IEEE Asian Test Symposium, 2011
  61. Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.;, “Static timing analysis for flexible TFT circuits,” Design Automation Conference (DAC), Jun. 2010
  62. Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M., “CSER: BISER-based concurrent soft-error resilience,” VLSI Test Symposium (VTS), Apr. 2010
  63. WC Wang and JCM Li, “Row-LFSR-Column (RLC) Test Response Masking Technique,” VLSI/CAD, 2010
  64. Wei-Che Wang and James C.-M. Lim Yi-Chih Sung, Amy Rao, and Laung-Terng Wang, “Test Response Compaction in the Presence of Many Unknowns,” VTTW, 2009
  65. Shang-Feng Chao, Jheng-Yang Ciou, and James Chien-Mo Li, “Transition Fault Diagnosis Using At-speed Test Patterns,” IEEE Int’l Workshop on RTL and High Level Testing, paper 5.3, 2009
  66. B. R. Chen and J. C.M. Li, “Bridging Fault Diagnosis to Identify the Layer of Systematic Defects,” Proc. IEEE Asian Test Symposium, paper 8B.2, 2009
  67. Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, J. C.-M. Li, I-Chun Cheng, “Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits,” Proc. IEEE Asian Test Symposium, paper 3C.4, 2009
  68. T.-F. Chien, W.-C. Chao, J. C.-M. Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “BIST Design Optimization for Large-Scale Embedded Memory Cores,” Proc. Int’l Conf. on Computer-Aided Design, 2009
  69. B. C. Bai, “Power Scan: DFT for Power Switches in VLSI Designs,” Proc. IEEE Int’l Test Conf., poster #7, 2009
  70. S.T. Shen, W. H. Liu, J. C. M Li, and I-Chun-Cheng, “Very-low Voltage Testing of TFT Circuits,” Proc. IEEE Int’l Test Conf., poster, 2009
  71. B. C. Bai, A. K Li, J. C.M. Li, and K. C. Wu, “Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs,” Proc. IEEE ASP-DAC, 2009
  72. Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li, “Diagnosis of Logic-chain Bridging Faults,” IEEE Int’l Workshop on RTL and High Level Testing, 2009
  73. T.-F. Chien, W.-C. Chao, J. C.-M. Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “BIST Design Optimization for Large-Scale Embedded Memory Cores,” Proc. Int’l Conf. on Computer-Aided Design, 2009
  74. G-M. Chiu and J. Li, “IEEE 1500-compatible Secure Test Wrapper for Embedded IP Cores,” IEEE Int’l Test Conf., PO#4, 2008
  75. Hsiu-Ting Lin, Jen-Yang Wen, James Li, Ming-Tung Chang, Min-Hsiu Tsai, Sheng-Chih Huang, Chih-Mou Tseng, “Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise,,” Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, PO#22, 2008
  76. W-C. Liu, J. Li, W-L. Tsai, H-T. Lin,, “Diagnosis of Logic-to-Chain Bridging Faults,” IEEE Int’l Test Conf., PO#16, 2008
  77. Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte, “On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using A Hybrid Single-Capture Scheme for Testing Scan Designs,” IEEE Int’l Symp. Proc. Defect and Fault Tolerant in VLSI Systems, 2008
  78. P.-C. Lin, C.-H. Hsu, J. C.-M. Li, C.-M. Chiang, and C.-J. Pan,, “Phase Noise Testing of Single Chip TV Tuners,,” IEEE VLSI-DAT, 2008
  79. C. H. Cheng, C.-H. Hsu , and J. C.M. Li, “An Asynchronous DFT Technique for TFT Macroelectronics,” International Symposium on Flexible Electronics and Display (ISFED), paper 4-6, 2008
  80. Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li, “Diagnosis of Logic-chain Bridging Faults,” IEEE Int’l Workshop on RTL and High Level Testing, paper 5.3, 2008
  81. C. H. Cheng, J. C.M. Li, “A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT Technology,” VLSI/CAD, 2008
  82. Shang-Feng Chao and J. C.-M. Li, “Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks,” VLSI/CAD, 2008
  83. Geng-Ming Chiu, C.-Y. Chiu, R-Y. Wen, and James Chien-Mo Li, “IEEE [1500 Compatible Secure Test Wrapper For Embedded IP Cores,” VTTW, 2008
  84. C.Y. Lee, H.M. Lin, F.M. Wang, and J. C. M. Li, “Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies,” IEEE Asian South Pacific Design Automation Conference (ASP-DAC), Jan. 2007
  85. B.-H. Chen, Wei-Chuang Kao, Bin-Chuan Bai, Shyue-Tsong Shen, James C.-M. Li, “Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique,” IEEE Asian Test Symposium, 2007
  86. Y. L Kao, W. S. Chuang, and J. C. M Li, “Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique,” IEEE Int'l Test Conf., Santa Clara, Oct. 2006
  87. Yu-Long Kao, Wei-Shun Chuang and J. C.-M. Li, “Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique,” VLSI/CAD, 2006
  88. Bo-Hua Chen and J. C.-M. Li, “CRC BIST: A Low Peak Power Self Technique,” VLSI/CAD, 2006
  89. H.M. Lin and J. C. M. Li, “Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains,” Proc. IEEE Int’l Test Conf., paper 42.3, Oct. 2005
  90. M.H. Chiu and J. C. M Li, “Jump Scan: A DFT Technique for Low Power Testing,,” Proc. IEEE VLSI Test Symposium, pp. 277-282, May 2005
  91. Lee, C-Y and Li, C-M, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” Asia Solid-State Circuit Conference (ASSCC), Taiwan, 2005
  92. C.Y. Lee and J. C. M. Li, “Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing,” IEEE Asian Solid State Circuit Conf., 2005
  93. P.C. Lin, J. C.-M. Li, Chih-Ming Chiang, and Chuo-Jan Pan, “Effective and Economic Phase Noise Testing for Single Chip TV Tuners,” VLSI/CAD Symposium, 2005
  94. Chun-Yi Lee and James Chien-Mo Li, “Segment Weighted Random BIST (SWR-BIST): A Low Power BIST Technique,” VLSI/CAD Symposium, 2005
  95. Yu-Te Liaw and James C.-M. Li, “A Two-level Test Data Compression and Test Time Reduction Technique for SOC,” VLSI/CAD Symposium, 2005
  96. E. J. McCluskey, A. Alyamani, J. C. M. Li, C. W. Tseng, E. Volkerink, F. F. Feriani, E. Li and S. Mitra, “ELF-Murphy Data on Defects and Test Sets,” Proc. IEEE VLSI Test Symposium, pp. 16-22, 2004
  97. L. W. Ko and C.M. Li, “Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique,” VLSI/CAD Symposium, pp.55, 2004
  98. C. K. Yo and C.M. Li, “Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation Patterns,” VLSI/CAD Symposium, pp.94, 2004
  99. Li, J. C.M. and E. J. McCluskey, “Diagnosis for Sequence Dependent Chips,” Proc. IEEE VLSI Test Symposium, pp.187-192, 2002
  100. C.W.Tseng, J.C.M. Li and E. J. McCluskey, “Experimental Results for Slow Speed Testing,” IEEE VLSI Test Symposium, 2002
  101. Mitra, S., C.W. Tseng, J. C. M Li, and E. J. McCluskey, “Pseudo Random Testing Theoretical Models vs. Real Data,” IEEE International Workshop on Test Resource Partitioning, 2001
  102. Li, J. C.M., Tseng, C.W. and E.J. McCluskey, “Testing for Resistive and Stuck Opens,” Proc. International Test Conference, pp. 1049-1058, 2001
  103. Li, J. C.M. and E.J. McCluskey, “Diagnosis of Tunneling Opens,” Proc. IEEE VLSI Test Symposium, pp.22-27, 2001
  104. Li, J. C.M and E.J. McCluskey, “Testing for Tunneling Opens,” Proc. International Test Conference, pp. 85-94, 2000

Books:

  1. J. C.-M. Li, and M. Hsiao, “Electronic Design Automation,” Morgan Kaufmann, 2009
  2. Wang, Wu, Wen and et. al., “VLSI Test Principles and Architectures,” Morgan Kaufmann, USA, 800 pages, 2006, ISBN:ISBN-10: 0123705975 and ISBN-13: 978-0123705976

Patents:

  1. J. Y. Wen and J. C. M. Li, “Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium,” 美國/中華民國專利申請中, 2010
  2. 王偉哲 李建模, “包含未知訊號之測試結果壓縮設計,” 中華民國專利申請中, 2009
  3. 鄭啟玄 李建模, “非同步電路可測試設計,” 中華民國專利 (專利號I 403745), Aug. 2008
  4. 邱銘豪 李建模, “跳躍式掃描: 低功率可測試設計,” 中華民國專利 (專利號265293), Dec. 2006