M.-L. Chiu, I.-F. Lo, and T.-H. Lin, “A Time-Domain Current-Mode Buck Converter with a PI Compensator Incorporating an Infinite Phase Shift Delay Line,” IEEE J. of Solid-State Circuits, vol. 60, no. 6, pp. 2206-2214, Jun. 2025
C.-Y. Lin, W.-H. Chen, Y.-T. Hung, T.-J. Wang, and T.-H. Lin, “An Area-Efficient Low-Jitter Fractional Output Divider with Replica-DTC-Free Background Calibration,” IEEE J. of Solid-State Circuits, vol. 59, no. 11, 3705-3715, Nov. 2024
W.-E. Lee and T.-H. Lin, “A 0.6-V 12-bit Set-and-Down SAR ADC With a DAC-Based Bypass Window Switching Method,” IEEE TCAS-2, 2023
C.-Y. Lin, Y.-W. Huang, and T.-H. Lin, “A Temperature-Compensated Crystal Oscillator with Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy from -30°C to 90°C,” IEEE TCAS-2, vol. 69, no. 4, 2016-2020, Apr. 2022
W.-E. Lee, C. Tsou, Z.-X. Liao, P.-Y. Lu, T.-H. Lin, S.-Y. Lee, C.-C. Lin, and G.-S. Shieh, “An Intelligent Wireless EEG Measurement System with Electrical and Optogenetic Stimulation for Epileptic Seizure Detection and Suppression,” IEEE Access, vol. 9, 80264-80274, 2021
C.-Y. Chiu, Z.-C. Zhang, and T.-H. Lin, “Design of a 0.6-V 429-MHz FSK Transceiver by Using Q-enhanced and Direct Power Transfer Techniques in 90-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 55, no. 11, 3024-3035, Nov. 2020
C.-C. Tu, Y.-K. Wang, and T.-H. Lin, “A Low-Noise Area-Efficient Chopped VCO-based CTDSM for Sensor Applications in 40-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 52, no. 10, pp. 2523-2532, Oct. 2017
C.-H. Weng, Y.-Y. Lin, and T.-H. Lin, “A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator with a Feedback-Assisted Quantizer,” IEEE TCAS-1, vol. 64, no. 5, pp. 1085-1093, May 2017
Y.-L. Tsai, C.-Y. Lin, B.-C. Wang, and T.-H. Lin, “A 330-uW 400-MHz BPSK Transmitter in 0.18-um CMOS for Bio-medical Applications,” IEEE TCAS-2, vol. 63, no. 5, pp. 448-452, May 2016
C.-H. Weng, T.-A. Wei, E. Alpman, C.-T. Fu, and T.-H. Lin, “A continuous-time delta-sigma modulator using ELD-compensation-embedded SAB and DWA-inherent time-domain quantizer,” IEEE J. of Solid-State Circuits, vol. 51 no. 5, pp. 1235-124, May 2016
C.-H. Weng, C.-K. Wu and T.-H. Lin, “A CMOS Thermistor- Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C2,” IEEE J. of Solid-State Circuits, vol. 50, no. 11, pp. 1-10, Nov. 2015
F.-C. Huang, M.-Y. Hsu, T.-H. Lin, and C.-K. Wang, “2.4-GHz Discrete-time Receiver without Subsampling Mixer,” IET Electronics Letters, vol. 50, no. 21, pp. 1549-1551, Oct. 2014
C.-C. Lin, C.-H. Weng, T.-A. Wei, Y.-Y. Lin, and T.-H. Lin, “A TDC-based Two-step Quantizer with Swapper Technique for a Multi-bit Continuous-time Delta-sigma Modulator,” IEEE TCAS-2, pp., 2014
Y.-J. Huang, C.-W. Huang, T.-H. Lin, C.-T. Lin, L.-G. Chen, P.-Y. Hsiao, B.-R. Wu, H.-T. Hsueh, B.-J. Kuo, H.-H. Tsai, H.-H. Liao, Y.-Z. Juang, C.-K. Wang, S.-S. Lu, “A CMOS cantilever-based label-free DNA SoC with Improved sensitivity for Hepatitis B Virus detection,” IEEE Transactions on Biomedical Circuits and Systems, pp. 820-831, Dec. 2013
Y.-H. Liu, L.-G. Chen, C.-Y. Lin, and T.-H. Lin, “A 650-pJ/bit MedRadio Transmitter with An FIR-Embedded Phase Modulator for Medical Micro-power Networks (MMNs),” IEEE TCAS-1, pp. 3279-3288, Dec. 2013
C.-W. Huang, H.-T. Hsueh, Y.-J. Huang, H.-H. Liao, H.-H. Tsai, Y.-Z. Juang, T.-H. Lin, S.-S. Lu, and C.-T. Lin, “A Fully Integrated Wireless CMOS Microcantilever Lab Chip for Detection of DNA from Hepatitis B Virus (HBV),” Sensors & Actuators: B. Chemical, pp. 867-873, Mar. 2013
C.-H. Weng, C.-C. Lin, Y.-C. Chang, and T.-H. Lin, “A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator with an Asynchronous Sequential Quantizer and Digital Excess Loop Delay Compensation,” IEEE TCAS-2, vol. 58, pp. 867-871, Dec. 2011
C.-Y. Ho, W.-S. Chan, Y.-Y. Lin, and T.-H. Lin, “A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for Tri-Mode GSM-Edge/UMTS/DVB-T Receivers with Power Scaling Technique,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 2571-2582, Nov. 2011
Tsung-Hsien Lin, Chao-Ching Chi, Wei-Hao Chiu, and Yu-Hsiang Huang, “A Synchronous 50% Duty-Cycle Clock Generator in 0.35-μm CMOS,” IEEE Transactions on VLSI, vol. 19, pp. 585-591, Apr. 2011
Y.-H. Liu and T.-H. Lin, “A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 2066-2079, Oct. 2010
W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, “A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1137-1149, Jun. 2010
Y.-H. Liu, C.-L. Li, and T.-H. Lin, “A 200-pJ/b MUX-based RF Transmitter for Implantable Multi-Channel Neural Recording,” IEEE T-MTT, vol. 57, pp. 2533-2541, Oct. 2009
Y.-H. Liu and T.-H. Lin, “A Wideband PLL-based G/FSK Transmitter in 0.18-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 2452-2462, Sept. 2009
T.-H. Lin, C.-L. Ti, and Y.-H. Liu, “Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs,” IEEE TCAS-1, vol. 56, pp. 877-885, May 2009
Y.-L. Tseng, H.-W. Chiu, T.-H. Lin, and F.-S. Jaw, “Miniature Modules for Multi-lead ECG Recording,” Biomedical Engineering: Applications, Basis and Communications, vol. 20, no. 4, pp. 219-222, 2008
T.-H. Lin, R.-L. Hsu, C.-L. Li, and Y.-C. Tseng, “A 5-GHz, 192.6-dBc/Hz/mW FOM, LC-VCO System with Amplitude Control Loop and LDO Voltage Regulator in 0.18-um CMOS,” IEEE Microwave and Wireless Component Letters, vol. 17, pp. 730-732, Oct. 2007
M.-C. Tsai and T.-H. Lin, “Design of a Continuous-Time 3rd-Order Delta-Sigma Modulator with Incremental Data Weighted Averaging,” International Journal of Electrical Engineering, vol. 14, pp.157-165, Jun. 2007
T.-H. Lin, C.-K. Wu, and M.-C. Tsai, “A 0.8-V 0.25-mW Current-Mirror OTA with 160-MHz GBW in 0.18-um CMOS,” IEEE TCAS-2, vol. 53, pp. 131-135, Feb. 2007
T.-H. Lin and Y.-J. Lai, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, pp. 340-349, Feb. 2007
T.-H. Lin and Y.-J. Lai, “A Time-Based Frequency Band Selection Method for Phase-Locked Loops,” IEE Electronics Letters, vol. 41, pp. 1279-1281, Nov. 2005
T.-H. Lin, W. J. Kaiser, and G. J. Pottie, “Integrated Low-Power Communication System Design for Wireless Sensor Networks,” IEEE Communications Magazine, vol. 42, pp. 142-150, Dec. 2004
A. Behzad, Z.M. Shi, S. Anand, L. Lin, K. Carter, M. Kappes, Tsung-Hsien (Eric) Lin, T. Nguyen, D. Yuan, S. Wu, Y.C. Wang, V. Fong, A. Rofougaran, “A 5-GHz Direct-Conversion CMOS Transceiver Utilizing Automatic Frequency Control for the IEEE 802.11a Wireless LAN Standard,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 2209-2220, Dec. 2003
T.-H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001
Conference & proceeding papers:
Y.-C. Liu, P.-H. Wang, Y.-Y. Huang, and T.-H. Lin, “A 66-82 GHz VCO with Dual-Tuning and Phase Noise Reduction Techniques in 40-nm CMOS,” IEEE RFIT, Aug. 2025
Y.-Y. Huang, P.-H. Wang, Y.-C. Liu, and T.-H. Lin, “A 0.8-V 80.7-GHz Dual-Core-Coupled Triple-Mode VCO in 40-nm CMOS,” IEEE RFIT, Aug. 2025
Y.-H. Wang, Y.-G. Yeh, and T.-H. Lin, “An 84.8-dB SNDR 62.5-kHz Bandwidth 2nd-order Noise-Shaping SAR ADC with a Duty-Cycled OTA Sharing Technique,” VLSI-TSA, Apr. 2025
C.-H. Fang, C.-Y. Lin, S. Yang, S.-C. Tsou, S.-H. Wen, K.-D. Chen, and T.-H. Lin, “A 185-μW, ±2.5-ppm -40°C-80°C Analog TCXO with A Differential-Pair-Based Polynomial Temperature Compensation Technique,” IEEE A-SSCC, Nov. 2024
P.-H. Wang, Y.-C. Liu, Y.-Y. Huang, W.-S. Hsu, Y.-L. Hsueh, Y.-H. Chung, and T.-H. Lin, “An 80-GHz Phase-Locked Loop for Millimeter-Wave Application in 40-nm CMOS,” IEEE APCCAS, Oct. 2024
S. Yang, T.-H. Chen, Y.-C. Wang, C.-H. Fang, C.-Y. Lin, S.-C. Tsou, S.-H. Wen, K.-D. Chen, and T.-H. Lin, “A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature Sensor,” ISOCC, Aug. 2024
C.-H. Chang, P.-C. Chen, H.-C. Cheng, J.-H. Chen, C.-Y. Lin, C.-T. Lin, and T.-H. Lin, “A VCO-Based Readout ADC for Quasi-Static Sensing Applications in 3-µm Low-Temperature Poly-Silicon Thin-Film Transistor Technology,” IEEE ISCAS, May 2024
M.-L. Chiu, I-F. Lo, and T.-H. Lin, “A Time-Domain CCM/DCM Current-Mode Buck Converter with a PI Compensator Incorporating an Infinite Phase Shift Delay Line,” IEEE ESSCIRC, Sept. 2023
C.-M. Chen, Y.-M. Hong and T.-H. Lin, “A Sub-Sampling Phase-Locked Loop with a Robust Agile-Locking Frequency-Locked Loop,” VLSI-TSA, Apr. 2023
Y.-M. Hong and T.-H. Lin, “A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop,” VLSI-TSA, Apr. 2023
C.-J. Tsai, I-F. Luo, T.-H. Lin, and C.-J. Chen, “An One-Cycle Load Transient Response and 0.81 mV/A Load-Regulation Time-Domain Cascaded-VCO-Controlled Buck Converter for Powering Gaming SoC,” IEEE A-SSCC, Nov. 2022
C.-L. Chen and T.-H. Lin, “An Open-loop VCO-based ADC with Quasi- Chopping and Non-linearity Cancellation for Bio-Sensor Applications,” IEEE BioCAS, Oct. 2022
C.-Y. Lin, Y.-W. Huang, and T.-H. Lin, “A ±20-ppm -50°C-105°C 1-μA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration,” IEEE A-SSCC, Nov. 2021
Y.-T. Chen, M.-L. Chiu, H.-W. Teng, and T.-H. Lin, “A Hybrid Supply Modulator for 10-MHz LTE Power Amplifier with 17.3% PAE Improvement,” VLSI-DAT, Apr. 2021
C.-Y. Lin, Y-T. Hung, T.-J. Wang, and T.-H. Lin, “A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms jitter Based on Replica-DTC-Free Background Calibration,” IEEE ISSCC, Feb. 2021
C.-A. Li, W.-E. Lee, C.-H. Lu, S.-Y. Lin, and T-H. Lin, “A Single-Comparator Active Rectifier with Auto-Calibration in 0.18-μm CMOS,” IEEE ISCAS, Oct. 2020
C.-Y. Lin, T.-J. Wang, Y.-T. Hung, and T.-H. Lin, “A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique,” VLSI-DAT, Aug. 2020
Z.-C. Zhang, C.-Y. Chiu, H.-C. Yuan, and T.-H. Lin, “A 0.5-V, 1.79-uW, 250-kbps Wake-up Receiver for IoT application in 90-nm CMOS,” VLSI-DAT, Aug. 2020
P.-Y. Li, W.-E. Lee, C.-T. Lin, L.-T. Wu, and T.-H. Lin, “A CMOS Temperature Sensor Based on a Chopped Continuous-Time Delta-Sigma Modulator,” VLSI-DAT, Aug. 2020
P.-H. Huang, C.-C. Tu, and T.-H. Lin, “An Area-Efficient VCO-based Hall Sensor Readout System for Autofocus Applications,” IEEE ISCAS, May 2019
M.-L. Chiu, T.-H. Yang, and T.-H. Lin, “A High Accuracy Constant-On-Time Buck Converter with Spur-Free On-Time Generator,” IEEE ISCAS, May 2019
D.-K. Lin, C.-C. Tu, S.-K. Kuo, and T.-H. Lin, “An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-um CMOS Process,” VLSI-DAT, Apr. 2019
C.-R. Lee, T.-W. Wang, Y.-L. Tsai, and T.-H. Lin, “A 0.5-V 400-MHz Transceiver Using Injection-Locked Techniques in 180-nm CMOS,” IEEE ICSICT, Nov. 2018
C.-Y. Lin, T.-J. Wang, and T.-H. Lin, “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator in 0.18-μm CMOS,” IEEE A-SSCC, Nov. 2017
C.-C. Tu, Y.-K. Wang, and T.-H. Lin, “A 0.06mm2 ±50mV Range -82dB THD Chopper VCO-based Sensor Readout Circuit in 40nm CMOS,” IEEE Symposium on VLSI Circuits, Jun. 2017
T.-Y. Chen, Y.-L. Tsai, and T.-H. Lin, “A Current Feedback Instrumentation Amplifier with Chopping and Dynamic Element Matching Techniques and Employing the Current-Reuse Technique in Input/Feedback Stages,” VLSI-DAT, Apr. 2017
C.-C. Tu, K.-C. Chen, T.-Y. Wu, and T.-H. Lin, “An Area-efficient Wideband CMOS Hall Sensor System for Camera Autofocus Systems,” IEEE A-SSCC, Nov. 2016
C.-Y. Lin and T.-H. Lin, “A 4-GHz Delta-Sigma Fractional-N Frequency Synthesizer with 2-Dimensional Quantization Noise Pushing and Fractional Spur Elimination Techniques,” IEEE A-SSCC, Nov. 2016
C.-C. Tu, Y.-K. Wang, and T.-H. Lin, “A 40-nV/√Hz 0.0145-mm2 Sensor Readout Circuit with Chopped VCO-based CTDSM in 40-nm CMOS,” IEEE A-SSCC, Nov. 2016
T.-W. Wang, Y.-L. Tsai, C.-R. Lee, F.-L. Hung, and T.-H. Lin, “A 0.5-V Sub-mW Energy-Efficient Receiver in 0.18-um CMOS for IoT Applications,” ISOCC, Oct. 2016
C.-H. Lu, J.-A. Li, and T.-H. Lin, “A 13.56-MHz Passive NFC Tag IC in 0.18-μm CMOS Process for Biomedical Applications,” VLSI-DAT, Apr. 2016
C.-H. Weng, W.-H. Huang, E. Alpman, and T.-H. Lin, “A 13-MHz 68-dB SNDR CTDSM Using SAB Loop Filter and Interpolating Flash Quantizer with Random-Skip IDWA Function in 90-nm CMOS,” IEEE A-SSCC, Nov. 2015
C.-H. Weng, T.-A. Wei and T.-H. Lin, “A 127 fJ/Conv. Continuous-Time Delta-Sigma Modulator with a DWA-Embedded Two-Step Time-Domain Quantizer,” VLSI-DAT, Apr. 2015
Y. -L. Tsai, F. -W. Lee, T. -Y. Chen, and T. -H. Lin, “A 2-channel −83.2dB crosstalk 0.061mm2 CCIA with an orthogonal frequency chopping technique,” IEEE ISSCC, Feb. 2015
C.-C. Tu, F. -Y. Lee and T. -H. Lin, “A 135 uW 0.46mOhm/rtHz Thoracic Impedance Variance Monitor with Square-Wave Current Modulation,” IEEE A-SSCC, Nov. 2014
C.-C. Tu, F. -Y. Lee and T. -H. Lin, “An Area-Efficient Capacitively-Coupled Instrumentation Amplifier with a Duty-Cycled Gm-C DC Servo Loop in 0.18-um CMOS,” IEEE A-SSCC, Nov. 2014
C.-H. Weng, C.-K. Wu and T.-H. Lin, “A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor with a Resolution of 0.01 °C,” IEEE A-SSCC, Nov. 2014
F.-C. Huang, S.-C. Hsu, Y.-L. Tsai, Y.-Y. Lin, and T.-H. Lin, “LMS-Based Digital Background Linearization Technique for VCO-Based Delta-Sigma ADC,” IEEE MWSCAS, Aug. 2014
Y.-L. Tsai, J.-Y. Chen, B.-C. Wang, T.-Y. Yeh, and T.-H. Lin, “A 400MHz 10Mbps D-BPSK Receiver with a Reference-less Dynamic Phase-to-Amplitude Demodulation Technique,” IEEE Symposium on VLSI Circuits, Jun. 2014
C.-H. Weng, T.-A. Wei, E. Alpman, C.-T. Fu, Y.-T. Tseng, and T.-H. Lin, “An 8.5MHz 67.2dB SNDR CTDSM with ELD Compensation Embedded Twin-T SAB and Circular TDC-based Quantizer in 90nm CMOS,” IEEE Symposium on VLSI Circuits, Jun. 2014
C.-C. Tu and T.-H. Lin, “Measurement and Parameter Characterization of Pseudo-Resistor Based CCIA for Biomedical Applications,” IEEE ISBB, Apr. 2014
C.-C. Tu and T.-H. Lin, “Analog Front-End Amplifier for ECG Applications with Feed-Forward EOS Cancellation,” VLSI-DAT, Apr. 2014
Y.-D. Chang, C.-H. Weng, T.-H. Lin, and C.-K. Wang, “A 379nW 58.5dB SNDR VCO-Based ΔΣ Modulator for Bio-Potential Monitoring,” IEEE Symposium on VLSI Circuits, pp. 66-67, Jun. 2013
T.-H. Lin and C.-Y. Lin, “Towards a Versatile Energy-Efficient Wireless Transmitter Design for Bio-medical Applications,” IEEE IWS, Apr. 2013
C.-C. Lin, C.-H. Weng, and T.-H. Lin, “A Low-Power Dual-Mode Continuous-Time Delta-Sigma Modulator with a Folded Quantizer,” VLSI-DAT, Apr. 2013
C.-Y. Lin, Y.-H. Liu, C.-T. Fu, H. Lakdawala, and T.-H. Lin, “An Energy-Efficient 2.4-GHz PSK/16-QAM Transmitter,” IEEE A-SSCC, pp. 361-364, Sept. 2012
Y.-C. Chuang, S.-L. Tsai, C.-E. Liu, and T.-H. Lin, “An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking,” IEEE A-SSCC, pp. 297-300, Sept. 2012
W.-N. Liu and T.-H. Lin, “An Energy-Efficient Ultra-Wideband Transmitter with an FIR Pulse-Shaping Filter,” VLSI-DAT, Apr. 2012
Y.-H. Liu, H.-H. Lo, and T.-H. Lin, “A 15-mW 2.4-GHz IEEE 802.15.4 Transmitter with a FIR-embedded Phase Modulator,” IEEE A-SSCC, pp. 281-284, Nov. 2011
Y.-C. Chang, W.-H. Chiu, C.-C. Lin, and T.-H. Lin, “A 4MHz BW 69dB SNDR Continuous-Time Delta-Sigma Modulator with Reduced Sensitivity to Clock Jitter,” IEEE A-SSCC, pp. 265-268, Nov. 2011
P.-Y. Hsiao, Y.-H. Liu, and T.-H. Lin, “An Energy-Efficient Super-Regenerative ASK Receiver with a DS-Based Pulse-Width Demodulator,” IEEE A-SSCC, pp. 369-372, Nov. 2011
C.-W. Huang, Y.-J. Huang, T.-H. Lin, C.-T. Lin, J.-K. Lee, L.-G. Chen, P.-Y. Hsiao, B.-R. Wu, H.-T. Hsueh, B.-J. Kuo, H.-H. Tsai, H.-H. Liao, Y.-Z. Juang, and S.-S. Lu, “An Integrated Microcantilever-Based Wireless DNA Chip for Hepatitis B Virus (HBV) DNA Detection,” MicroTAS, Oct. 2011
W.-H. Chiu and T.-H. Lin, “A 3.6GHz 1MHz-Bandwidth Delta-Sigma Fractional-N PLL with a Quantization-Noise Shifting Architecture in 0.18um CMOS,” IEEE Symposium on VLSI Circuits, pp. 114-115, Jun. 2011
Y.-J. Huang, C.-W. Huang, T.-H. Lin, C.-T. Lin, L.-G. Chen, P.-Y. Hsiao, B.-R. Wu, H.-T. Hsueh, B.-J. Kuo, H.-H. Tsai, H.-H. Liao, Y.-Z. Juang, C.-K. Wang, and S.-S. Lu, “A Fully-integrated Cantilever-based DNA Detection SoC in a CMOS Bio-MEMS Process,” IEEE Symposium on VLSI Circuits, pp. 50-51, Jun. 2011
C.-K. Wu, W.-S. Chan, and T.-H. Lin, “A 80kS/s 36uW Resistor-based Temperature Sensor using BGR-free SAR ADC with a Unevenly-weighted Resistor String in 0.18μm CMOS,” IEEE Symposium on VLSI Circuits, pp. 222-223, Jun. 2011
C.-Y. Ho, Y.-Y. Lin, and T.-H. Lin, “A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for Tri-Mode GSM-Edge/UMTS/DVB-T Receivers with Power Scaling Technique,” IEEE A-SSCC, pp. 145-148, Nov. 2010
W.-N. Liu and T.-H. Lin, “A 100 Mbps, 14.3 pJ/bit Ultra-Wideband Transmitter with Pulse-Shaping FIR Filter,” VLSI Design/CAD Symposium, pp. 439-442, Aug. 2010
C.-H. Weng, Y.-L. Tsai, and T.-H. Lin, “A Digitally-Assisted Excess Loop Delay Compensation Technique for Continuous-Time Delta-Sigma Modulators,” VLSI Design/CAD Symposium, pp. 530-533, Aug. 2010
T.-C. Chen, T.-H. Lee, Y.-H. Chen, T.-C. Ma, T.-D. Chuang, C.-J. Chou, C.-H. Yang, T.-H. Lin, and L.-G. Chen, “1.4μW/channel 16-channel EEG/ECoG Processor for Smart Brain Sensor SoC,” IEEE Symposium on VLSI Circuits, pp. 21-22, Jun. 2010
W.-H. Chiu, C.-Y. Cheng, and T.-H. Lin, “A 5-GHz Relative-Phase Cancellation Fractional-N Phase-Locked Loops in 0.13-um CMOS,” IEEE ISCAS, pp. 2996-2999, May 2010
C.-Y. Ho, Y.-Y. Lin, and T.-H. Lin, “Dual-Mode Continuous-Time Quadrature Bandpass DS Modulator with Pseudo-random Quadrature Mismatch Shaping Algorithm for Low-IF Receiver Application,” IEEE ISCAS, pp. 25-28, May 2010
C.-J. Chou, B.-J. Kuo, and T.-H. Lin, “A 1-V Low-Noise Readout Front-End for Biomedical Applications in 0.18-um CMOS,” VLSI-DAT, pp. 295-298, Apr. 2010
H.-H. Liu, C.-J. Tung, Y.-H. Liu, and T.-H. Lin, “A 400-MHz Super-Regenerative Receiver with a Fast Digital Frequency Calibration,” VLSI-DAT, pp. 54-57, Apr. 2010
W.-H. Chiu, T.-S. Chang, and T.-H. Lin, “A Charge Pump Current Calibration Technique for DS Fractional-N PLLs in 0.18-um CMOS,” IEEE A-SSCC, pp. 73-76, Nov. 2009
K.-C. Liao, P.-S. Huang, W.-H. Chiu, and T.-H. Lin, “A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-um CMOS,” IEEE A-SSCC, pp. 353-356, Nov. 2009
C.-H. Yang, W.-H. Chiu, and T.-H. Lin, “A Time-Domain-Based Self-Calibrated Analog-to-Digital Converter With A Linear Voltage-to-Delay Circuit in 0.18-um CMOS,” VLSI Design/CAD Symposium, Aug. 2009
Y.-H. Liu, H.-H. Liu, and T.-H. Lin, “A Super-Regenerative ASK Receiver with Delta-Sigma Pulse-width Digitizer and SAR-based Fast Frequency Calibration for MICS Applications,” IEEE Symposium on VLSI Circuits, pp. 38-39, Kyoto, Japan, Jun. 2009
W.-H. Chiu, Y.-H. Huang, and T.-H. Lin, “A 5GHz Phase-Locked Loop Using Dynamic Phase-Error Compensation Technique for Fast Settling in 0.18-um CMOS,” IEEE Symposium on VLSI Circuits, pp. 128-129, Kyoto, Japan, Jun. 2009
Y.-H. Liu and T.-H. Lin, “A 3.5-mW 15-Mbps O-QPSK Transmitter for Real-time Wireless Medical Imaging Applications,” IEEE CICC, pp. 599-602, San Jose, CA, USA, Sept. 2008
C.-L. Ti, Y.-H. Liu, and T.-H. Lin, “A 2.4-GHz Fractional-N PLL with a PFD/CP Linearization and an Improved CP Circuit,” IEEE ISCAS, pp. 1728-1731, May 2008
Y.-C. Chen, W.-H. Chiu, and T.-H. Lin, “A 120-MHz Active-RC Filter with an Agile Frequency Tuning Scheme in 0.18-um CMOS,” VLSI-DAT, pp. 208-211, Apr. 2008
C.-J. Tung, Y.-H. Liu, and T.-H. Lin, “A 400-MHz Super-Regenerative Receiver with Digital Calibration for Capsule Endoscope Systems in 0.18-um CMOS,” VLSI-DAT, pp. 43-46, Apr. 2008
W.-H. Chiu, T.-S. Chan, and T.-H. Lin, “A 5.5-GHz 16-mW Fast-Locking Frequency Synthesizer in 0.18-µm CMOS,” IEEE A-SSCC, pp. 456-459, Nov. 2007
Y.-H. Liu and T.-H. Lin, “An Energy-Efficient 1.5-Mbps Wireless FSK Transmitter with A Sigma Delta-Modulated Phase Rotator,” IEEE ESSCIRC, Sept. 2007
W.-H. Chiu and T.-H. Lin, “A Wide-Range Synchronous 50% Duty-Cycle Clock Generator,” 18th VLSI Design/CAD Symposium, Aug. 2007
C.-L. Ti and T.-H. Lin, “A 2.4-GHz 18-mW Two-Point Delta-Sigma Modulation Transmitter for IEEE 802.15.4,” VLSI-DAT, 188-191, Apr. 2007
B. Marholev, M. Pan, E. Chien, L. Zhang, R. Roufoogaran, S. Wu, I. Bhatti, T.-H. Lin, M. Kappes, S. Khorram, S. Anand, A. Zolfaghari, J. Castaneda, C.M. Chien, B. Ibrahim, H. Jensen, H. Kim, P. Lettieri, S. Mak, J. Lin, Y.C. Wong, R. Lee, M. Sye, M. Rofou, “A Single-Chip Bluetooth EDR Device in 0.13um CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 558-559, Feb. 2007
Y.-H. Liu, C.-J. Tung, and T.-H. Lin, “A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for Medical Imaging,” IEEE BioCAS Conf., pp. 162-165, Dec. 2006
W.-C. Fang and T.-H. Lin, “Low-Power Radio Design for Wireless Smart Sensor Networks,” IEEE International Workshop on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), pp. 583-586, Dec. 2006
T.-H. Lin and C.-C. Chi, “A 70-490 MHz 50% Duty-Cycle Correction Circuit in 0.35-um CMOS,” IEEE A-SSCC, pp. 91-94, Nov. 2006
C.-K. Wu, M.-C. Tsai, and T.-H. Lin, “A 0.8-V 0.25-mW Current-Mirror OTA with 160-MHz GBW in 0.18-um CMOS,” VLSI Design/CAD Symposium, pp. 545-548, Aug. 2006
M.-C. Tsai and T.-H. Lin, “A 3rd-Order Multi-bit Continuous-Time Sigma-Delta Modulator with Incremental Data Weighted Averaging,” VLSI Design/CAD Symposium, pp. 353-356, Aug. 2006
R.-L. Syu, C.-L. Li, and T.-H. Lin, “A 5-GHz CMOS Frequency Synthesizer with Triode Regime Biased LC-VCO for Low Phase Noise,” VLSI Design/CAD Symposium, pp. 125-128, Aug. 2006
Y.-J. Lai and T.-H Lin, “A 10-GHz CMOS PLL with an Agile VCO Calibration,” IEEE A-SSCC, pp. 213-216, Nov. 2005
A. Behzad, E. Lin, K. Carter, M. Kappes, Z.M. Shi, L. Lin, S. Wu, S. Anand, T. Nguyen, D. Yuan, Y.C. Wong, V. Fong, B. Yeung, and A. Rofougaran, “A 4.92-5.845GHz Direct-Conversion CMOS Transceiver for IEEE 802.11a Wireless LAN,” IEEE RFIC Symposium, pp. 335-338, Jun. 2004
H.-M. Chien, T.-H. Lin, B. Ibrahim, L. Zhang, M. Rofougaran, A. Rofougaran, and W. J. Kaiser, “A 4GHz Fractional-N Synthesizer for IEEE 802.11a,” IEEE Symposium on VLSI Circuits, pp. 46-49, Jun. 2004
A. Behzad, L. Lin, Z.M. Shi, S. Anand, K. Carter, M. Kappes, E. Lin, T. Nguyen, D. Yuan, S. Wu, Y.C. Wang, V. Fong, A. Rofougaran, “Direct-Conversion CMOS Transceiver with Automatic Frequency Control for 802.11a Wireless LANs,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 356-357, Feb. 2003
H. Darabi, J. Chiu, S. Khorram, H. Kim, Z. Zhou, E. Lin, S. Jiang, K. Evans, E. Chien, B. Ibrahim, E. Geronaga, L. Tran, R. Rofougaran, “A Dual Mode 802.11b/Bluetooth Radio in 0.35um CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 86-87, Feb. 2003
T.-H. Lin and W. J. Kaiser, “A 900MHz, 2.5mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE CICC, pp. 375-378, May 2000
R. Rofougaran, T.-H. Lin, and W. J. Kaiser, “CMOS Front-End LNA-Mixer for Micropower RF Wireless Systems,” IEEE ISLPED, pp. 238-242, Aug. 1999
W. Fang and E. Lin, “A Low-Power VLSI Neural Processor Design for Image Data Compression in a SOI CMOS Technology,” Intl. Conf. on Integrated Micro/Nanotechnology for Space Applications, Mar. 1999
G. Asada, I. Bhatti, T.-H. Lin, S. Natkunanthanan, F. Newberg, R. Rofougaran, A. Sipos, S. Valoff, G. J. Pottie, and W. J. Kaiser, “Wireless Integrated Network Sensors (WINS),” SPIE, pp. 11-18, Mar. 1999
G. Asada, M. Dong, T.-H. Lin, F. Newberg, G. Pottie, H. O. Marcy, and W. J. Kaiser, “Wireless Integrated Network Sensors: Low Power Systems on a Chip,” IEEE ESSCIRC, pp. 9-16, Aug. 1998
T.-H. Lin, H. Sanchez, R. Rofougaran, and W. J. Kaiser, “Micropower CMOS RF Components for Distributed Wireless Sensors,” IEEE RFIC Symposium, pp. 157-160, Jun. 1998
G. Asada, I. Bhatti, T.-H. Lin, S. Natkunanthanan, F. Newberg, R. Rofougaran, A. Sipos, S. Valoff, G. J. Pottie, and W. J. Kaiser, “Wireless Integrated Network Sensors (WINS),” SPIE, pp. 11-18, Mar. 1998
Books:
Yao-Hong Liu and Tsung-Hsien Lin, “Integrated Microsystems: Electronics, Photonics and Biotechnology; Chapter 4: Design of a Low-power Dual-mode MUX-based Transmitter for Bio-medical Applications,” Taylor & Francis, Sept. 2011
Patents:
Yi-Lin Tsai, Fong-Wen Lee, Chih-Chan Tu, Bang-Cyuan Wang, Tsung-Hsien Lin, “Biomedical signal sensing circuit,” US Patent No. 9,833,195, Dec. 2017
C.-H. Weng, C.-K. Wu, and T.-H. Lin, “Analog-to-digital converting circuit with temperature sensing and electronic device thereof,” US Patent No. 8,957,797, Feb. 2015
Tsung-Hsien Lin, Chen-En Liu, Chen-Chien Liu, Wei-Hou Chiu, and Sung-Lin Tsai, “Frequency tracing circuit and method thereof,” US Patent No. 8,824,615, Sept. 2014
Yi-Lin Tsai, Jian-You Chen, Bang-Cyuan Wang, and Tsung-Hsien Lin, “Receiver, signal demodulation module and demodulation method thereof,” US Patent No. 8,811,541, Aug. 2014
Tsung-Hsien Lin, Wei-Hao Chiu, and Yu-Hsiang Huang, “Phase locked loop capable of fast locking,” US Patent No. 8,437,441, Jul. 2013
Tsung-Hsien Lin and Yu-Yu Chen, “Modulator with loop delay compensation,” US Patent No. 8,072,362, Dec. 2011
Tsung-Hsien Lin and Yu-Yu Chen, “Bandpass delta-sigma modulator,” US Patent No. 8,004,437, Aug. 2011
Tsung-Hsien Lin, Chung-Hsing Yang, and Wei-Hou Chiu, “Voltage-to-time converter, and voltage-to-digital converting device,” US Patent No. 7,916,064, Mar. 2011
Yao-Hong Liu and Tsung-Hsien Lin, “Frequency Shift Keying Modulator Having Sigma-Delta Modulated Phase Rotator,” US Patent No. 7,667,551, Feb. 2010
Chan-Hsiang Weng and Tsung-Hsien Lin, “Delta sigma modulator and method for compensating delta sigma modulators for loop delay,” US Patent No. 7,535,392, May 2009
Tsung-Hsien Lin and Hung-Ming Chien, “Linearized fractional-N synthesizer having a gated offset,” US Patent No. 7,289,782, Oct. 2007
Tsung-Hsien Lin,, “Clock generator having a 50% duty-cycle,” US Patent No. 7,250,802, Jul. 2007
Tsung-Hsien Lin, “Calibration of a Phase Locked Loop,” US Patent No. 7,174,144, Feb. 2007
Tsung-Hsien Lin, “An Analog Open-Loop VCO Calibration Method,” US Patent No. 7,099,643, Aug. 2006
Hung-Ming Chien and Tsung-Hsien Lin, “Linearized Fractional-N Synthesizer with Fixed Charge Pump Offset,” US Patent No. 7,082,176, Jul. 2006
Tsung-Hsien Lin, “High Speed Differential Signaling Logic Gate and Applications Thereof,” US Patent No. 6,998,877, Feb. 2006
Tsung-Hsien Lin and Hung-Ming Chien, “Linearized Fractional-N Synthesizer Having a Gated Offset,” US Patent No. 6,985,708, Jan. 2006